Michael Frank

PERFORMING TRANSACTION AGGREGATION WITH AN AGGREGATOR IN A NETWORK-ON-CHIP (NoC)

SYSTEM AND METHOD FOR MANAGING EVENT MESSAGES IN A CACHE COHERENT INTERCONNECT

System and method to enter and exit a cache coherent interconnect

System and method for event messages in a cache coherent interconnect

NETWORK-ON-CHIP (NoC) USING DEADLINE BASED ARBITRATION

Queue management system, starvation and latency management system, and methods of use

Compensating for aging in integrated circuits

Streaming wavelet transform

Execution units for implementation of context adaptive binary arithmetic coding (CABAC)

Master synchronization for multiple displays

Compensating for aging in integrated circuits

Cache Device and Methods Thereof

Memory compression technique with low latency per pixel

Color Space Conversion for Mirror Mode

Image sensor having HDR capture capability

Modifying operating parameters based on device use

Collecting information regarding electronic aging of products

Modifying operating parameters of a device based on aging information

Method and apparatus to increase bit-depth on gray-scale and multi-channel images (inverse dithering)

Devices and methods for dynamic dithering

Devices and methods for obtaining high-local-contrast image data

Master synchronization for multiple displays

Fabric limiter circuits

Hierarchical fabric control circuits

Switching a PLL clock source to reduce wireless communication interference

Adjusting PLL clock source to reduce wireless communication interference

Memory read timing margin adjustment for a plurality of memory arrays according to predefined delay tables

Prefetch instruction that ignores a cache hit

Color Space Conversion for Efficient Filtering

Memory compression technique with low latency per pixel

Electronic age detection circuit

Compensating for aging in integrated circuits

Integrated circuit having secure access to test modes

Execution units for context adaptive binary arithmetic coding (CABAC)

Computing system having CPU and bridge operating using CPU frequency

Processor instructions for improved AES encryption and decryption

Method of integrating a personal computing system and apparatus thereof

Processor with coprocessor interfacing functional unit for forwarding result from coprocessor to retirement unit

Method and apparatus for decompression of block compressed data

Method and apparatus for decoding variable length data

Transient transactional cache

Unified Processor Architecture For Processing General and Graphics Workload

Three operand instruction extension for X86 architecture

Video imaging system including a digital image sensor and a digital signal processor

Optical package for image sensor with integrated heater

Removal of stationary noise pattern from digital images

Multi-standard video image capture device using a single CMOS image sensor

Removal of stationary noise pattern from digital images

Digital CMOS image sensor incorporating a programmable multi-functional lookup table

Digital drive architecture for flat panel displays

System for handling memory requests and method thereof

Fixed pattern noise subtraction in a digital image sensor

Tone correction method using a blending mask

Image processor with noise reduction circuit

Image sensor and method for implementing optical summing using selectively transmissive filters

System for handling memory requests and method thereof

Method and apparatus for configuring an integrated bus

Automatic detection of fluorescent flicker in video images

Using a time invariant statistical process variable of a semiconductor chip as the chip identifier