Crossbar, Inc.

Resistive switching memory having confined filament formation and methods thereof

Error correction for identifier data generated from unclonable characteristics of resistive memory

Utilizing two-terminal resistive switching memory to store validation data of an integrated circuit device

Parameterized key size for CSP address table mapping in secure microcontroller with unified RRAM

Link table for characterizing multi-mode CSP parameters in a secure microcontroller with unified RRAM

Monotonic counter implemented in non-volatile resistive switching memory

CRYPTOCURRENCY HARDWARE WALLET ON MONOLITHIC CHIP WITH COMMON PHYSICAL COUNTERMEASURES AND SECURE MEMORY

Differential programming of two-terminal resistive switching memory with program soaking and adjacent path disablement

Secure circuit integrated with memory layer

Cell cycling to minimize resistive memory random number correlation

FLEXIBLE AND CONFIGURABLE BIT ERROR RATE REDUCTION FOR NON-VOLATILE MEMORY

Differential programming of two-terminal resistive switching memory with intrinsic error suppression

ERASE ALGORITHM WITH A WEAK PROGRAM PULSE FOR NON-VOLATILE MEMORY

Dynamic host allocation of physical unclonable feature operation for resistive switching memory

Differential programming of two-terminal resistive switching memory with program soaking and adjacent path disablement

Generating physical unclonable function data from a transistor of a semiconductor device

Differential programming of two-terminal memory with intrinsic error suppression and wordline coupling

Differential programming of two-terminal memory with program detection and multi-path disablement

Error correction for identifier data generated from unclonable characteristics of resistive memory

Reverse programmed resistive random access memory (RAM) for one time programmable (OTP) applications

Cell cycling to minimize resistive memory random number correlation

Configuration bit using RRAM

Non-stoichiometric resistive switching memory device and fabrication methods

Distinct chip identifier sequence utilizing unclonable characteristics of resistive memory on a chip

Resistive switching memory having confined filament formation and methods thereof

Resistive switching memory devices and method(s) for forming the resistive switching memory devices

Formation of structurally robust nanoscale Ag-based conductive structure

Physically unclonable function (PUF) generation involving programming of marginal bits

Physically unclonable function (PUF) generation involving high side programming of bits

Computing memory architecture

Capacitance measurement and apparatus for resistive switching memory devices

Secure circuit integrated with memory layer

Distinct chip identifier sequence utilizing unclonable characteristics of resistive memory on a chip

Resistive random access memory erase techniques and apparatus

Distinct chip identifier sequence utilizing unclonable characteristics of resistive memory on a chip

Distinct chip identifier sequence utilizing unclonable characteristics of resistive memory on a chip

Distinct chip identifier sequence utilizing unclonable characteristics of resistive memory on a chip

Distinct chip identifier sequence utilizing unclonable characteristics of resistive memory on a chip

Selector device for two-terminal memory

Using aluminum as etch stop layer

Resistive random-access memory and architecture with select and control transistors

Non-volatile memory bank with embedded inline computing logic

Method for fabricating an array of 4F2 resistive non-volatile memory in a NAND architecture

State change detection for two-terminal memory

Memory stack liner comprising dielectric block layer material

Resistive random access memory and fabrication techniques

Cache management for memory module comprising two-terminal resistive memory

Non-volatile memory cell utilizing volatile switching two terminal device and a MOS transistor

Neuromorphic logic for an array of high on/off ratio non-volatile memory cells

Formation of structurally robust nanoscale Ag-based conductive structure

Read operation with data latch and signal termination for 1TNR memory array

4F2 resistive non-volatile memory formed in a NAND architecture

Logical to physical translation for two-terminal memory

Resistive random access memory program and erase techniques and apparatus

Network router device with hardware-implemented lookups including two-terminal non-volatile memory

Programmable logic applications for an array of high on/off ratio and high speed non-volatile memory cells

Memory device including integrated deterministic pattern recognition circuitry

Selector device for two-terminal memory

Computing memory architecture

Resistive random access memory matrix multiplication structures and methods

Write distribution techniques for two-terminal memory wear leveling

Multiple-bank memory device with status feedback for subsets of memory banks

Non-volatile memory cell utilizing volatile switching two terminal device and a MOS transistor

Threshold voltage tuning for a volatile selection device

State change detection for two-terminal memory utilizing current mirroring circuitry

Semiconductor device for a non-volatile (NV) resistive memory and array structure for an array of NV resistive memory

Switching block configuration bit comprising a non-volatile memory cell

Reduced write status error polling for non-volatile resistive memory device

Memory apparatus with non-volatile two-terminal memory and expanded, high-speed bus

Read operation with data latch and signal termination for 1TNR memory array

Two-terminal memory electrode comprising a non-continuous contact surface

Selector device for two-terminal memory

Switching block configuration bit comprising a non-volatile memory cell

Flatness of memory cell surfaces

Field programmable gate array utilizing two-terminal non-volatile memory

Multi-buffered shift register input matrix to FPGA

Node retainer circuit incorporating RRAM

Non-volatile write and read cache for storage media

Multi-bank non-volatile memory apparatus with high-speed bus

Page management for data operations utilizing a memory device

Resistive memory cell with intrinsic current control

Liner layer for dielectric block layer

Selector device for two-terminal memory

Non-volatile resistive memory configuration cell for field programmable gate array

Enhanced erasing of two-terminal memory

Enhanced MLC programming

Using aluminum as etch stop layer

Selector device for two-terminal memory

Monolithically integrated resistive memory using integrated-circuit foundry compatible processes

Two-terminal memory set features type mechanisms enhancements

Sensing a non-volatile memory device utilizing selector device holding characteristics

Two-terminal memory compatibility with NAND flash memory set features type mechanisms

Monolithic memory comprising 1T1R code memory and 1TnR storage class memory

Device switching using layered device structure

Regulating interface layer formation for two-terminal memory

Programmable logic applications for an array of high on/off ratio and high speed non-volatile memory cells

State change detection for two-terminal memory during application of a state-changing stimulus

Enhanced programming of two-terminal memory

Wear leveling and improved efficiency for a non-volatile memory device

Sub-oxide interface layer for two-terminal memory