San Jose, California
United States
132
2020-12-10
129
2022-04-05
These are the the leading inventors for applications assigned to PDF Solutions, Inc.:
PDF Solutions, Inc. based in San Jose, US has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:
Maintenance scheduling for semiconductor manufacturing equipment
#2 | 2020-04-14 ✅ Patent 10,622,344 granted on 2020-04-14IC chips containing a mixture of standard cells obtained from an original set of design rules and enhanced standard cells that are a substantially uniform variant of the original set of design rules and methods for making the same
#3 | 2020-01-07 ✅ Patent 10,529,631 granted on 2020-01-07Test structures and method for electrical measurement of FinFET fin height
#4 | 2019-08-13 ✅ Patent 10,380,305 granted on 2019-08-13Direct probing characterization vehicle for transistor, capacitor and resistor testing
#5 | 2019-04-23 ✅ Patent 10,268,562 granted on 2019-04-23Advanced manufacturing insight system for semiconductor application
#6 | 2018-10-23 ✅ Patent 10,109,539 granted on 2018-10-23Integrated circuit including NCEM-enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
#7 | 2018-10-16 ✅ Patent 10,102,330 granted on 2018-10-16Method for automatically determining proposed standard cell design conformance based upon template constraints
#8 | 2018-10-09 ✅ Patent 10,096,530 granted on 2018-10-09Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells
#9 | 2018-10-09 ✅ Patent 10,096,529 granted on 2018-10-09Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including metal island open configured fill cells
#10 | 2018-05-29 ✅ Patent 9,984,970 granted on 2018-05-29Advanced node standard logic cells that utilizes TS cut mask(s) and avoid DFM problems caused by closely spaced gate contacts and TSCUT jogs
#11 | 2018-05-29 ✅ Patent 9,984,944 granted on 2018-05-29Integrated circuit containing DOEs of GATECNT-tip-to-side-short-configured, NCEM-enabled fill cells
#12 | 2018-04-24 ✅ Patent 9,953,889 granted on 2018-04-24Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of GATECNT-GATE via opens
#13 | 2018-04-24 ✅ Patent 9,952,268 granted on 2018-04-24Method for accurate measurement of leaky capacitors using charge based capacitance measurements
#14 | 2018-04-19 ✅ Patent 10,546,792 granted on 2020-01-28Method for manufacturing a semiconductor product wafer
#15 | 2018-04-17 ✅ Patent 9,947,601 granted on 2018-04-17Integrated circuit including NCEM-enabled, side-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
#16 | 2018-03-27 ✅ Patent 9,929,063 granted on 2018-03-27Process for making an integrated circuit that includes NCEM-Enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
#17 | 2018-03-27 ✅ Patent 9,929,136 granted on 2018-03-27Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-Enabled fill cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including chamfer short configured fill cells
#18 | 2018-03-20 ✅ Patent 9,922,890 granted on 2018-03-20Integrated circuit including NCEM-enabled, snake-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
#19 | 2018-03-20 ✅ Patent 9,922,968 granted on 2018-03-20Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including chamfer short configured fill cells
#20 | 2018-03-06 ✅ Patent 9,911,670 granted on 2018-03-06Integrated circuit including NCEM-enabled, via-open/resistance-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gate
#21 | 2018-03-06 ✅ Patent 9,911,669 granted on 2018-03-06Integrated circuit including NCEM-enabled, diagonal gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
#22 | 2018-03-06 ✅ Patent 9,911,668 granted on 2018-03-06Integrated circuit including NCEM-enabled, corner gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
#23 | 2018-03-06 ✅ Patent 9,911,649 granted on 2018-03-06Process for making and using mesh-style NCEM pads
#24 | 2018-02-27 ✅ Patent 9,905,553 granted on 2018-02-27Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cells
#25 | 2018-02-27 ✅ Patent 9,905,487 granted on 2018-02-27Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of V0 via opens
#26 | 2018-02-20 ✅ Patent 9,899,276 granted on 2018-02-20Process for making an integrated circuit that includes NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
#27 | 2018-01-30 ✅ Patent 9,881,843 granted on 2018-01-30Integrated circuit including NCEM-Enabled, tip-to-tip gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
#28 | 2018-01-16 ✅ Patent 9,870,962 granted on 2018-01-16Integrated circuit including NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
#29 | 2018-01-16 ✅ Patent 9,871,028 granted on 2018-01-16Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including tip-to-tip short configured fill cells, and the second DOE including chamfer short configured fill cells
#30 | 2018-01-16 ✅ Patent 9,870,966 granted on 2018-01-16Process for making semiconductor dies, chips and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of AACNT-TS via opens
#31 | 2018-01-16 ✅ Patent 9,870,441 granted on 2018-01-16Snap-to valid pattern system and method
#32 | 2018-01-09 ✅ Patent 9,865,583 granted on 2018-01-09Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including stitch open configured fill cells
#33 | 2017-12-19 ✅ Patent 9,847,264 granted on 2017-12-19Method for manufacturing a semiconductor product wafer
#34 | 2017-11-28 ✅ Patent 9,831,141 granted on 2017-11-28Integrated circuit containing DOEs of GATE-snake-open-configured, NCEM-enabled fill cells
#35 | 2017-11-21 ✅ Patent 9,825,018 granted on 2017-11-21Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including tip-to-tip short configured fill cells, and the second DOE including chamfer short configured fill cells
#36 | 2017-11-14 ✅ Patent 9,818,660 granted on 2017-11-14Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including metal island open configured fill cells
#37 | 2017-11-14 ✅ Patent 9,818,738 granted on 2017-11-14Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells with first DOE including tip-to-side short configured fill cells and second DOE including chamfer short configured fill cells
#38 | 2017-10-31 ✅ Patent 9,805,994 granted on 2017-10-31Mesh-style NCEM pads, and process for making semiconductor dies, chips, and wafers using in-line measurements from such pads
#39 | 2017-10-26 ✅ Patent 10,852,337 granted on 2020-12-01Test structures for measuring silicon thickness in fully depleted silicon-on-insulator technologies
#40 | 2017-10-24 ✅ Patent 9,799,640 granted on 2017-10-24Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells
#41 | 2017-10-17 ✅ Patent 9,793,253 granted on 2017-10-17Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least Via-open-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured NCEM-enabled fill cells
#42 | 2017-10-10 ✅ Patent 9,786,650 granted on 2017-10-10Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including metal island open configured fill cells
#43 | 2017-10-10 ✅ Patent 9,786,649 granted on 2017-10-10Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including stitch open configured fill cells
#44 | 2017-10-10 ✅ Patent 9,785,496 granted on 2017-10-10Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on wafers that include multiple steps for enabling NC detecteion of AACNT-TS via opens
#45 | 2017-10-10 ✅ Patent 9,786,648 granted on 2017-10-10Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cells
#46 | 2017-10-03 ✅ Patent 9,778,974 granted on 2017-10-03Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including metal island open configured fill cells
#47 | 2017-10-03 ✅ Patent 9,780,083 granted on 2017-10-03Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, TS-short-configured, metal-short configured, and AA-short-configured, NCEM-enabled fill cells
#48 | 2017-09-26 ✅ Patent 9,773,775 granted on 2017-09-26Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including snake open configured fill cells
#49 | 2017-09-26 ✅ Patent 9,773,774 granted on 2017-09-26Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells
#50 | 2017-09-26 ✅ Patent 9,773,773 granted on 2017-09-26Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATE-short-configured, and GATECNT-short-configured, NCEM-enabled fill cells
#51 | 2017-09-19 ✅ Patent 9,766,970 granted on 2017-09-19Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including metal island open configured fill cells
#52 | 2017-09-19 ✅ Patent 9,768,083 granted on 2017-09-19Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including snake open configured fill cells
#53 | 2017-09-19 ✅ Patent 9,768,156 granted on 2017-09-19Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including chamfer short configured fill cells
#54 | 2017-09-12 ✅ Patent 9,761,502 granted on 2017-09-12Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including merged-via configured fill cells
#55 | 2017-09-12 ✅ Patent 9,761,575 granted on 2017-09-12Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured, NCEM-enabled fill cells
#56 | 2017-09-12 ✅ Patent 9,761,574 granted on 2017-09-12Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATECNT-short-configured, metal-short-configured, and AA-short-configured, NCEM-enabled fill cells
#57 | 2017-09-12 ✅ Patent 9,761,573 granted on 2017-09-12Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured, NCEM-enabled fill cells
#58 | 2017-08-29 ✅ Patent 9,748,153 granted on 2017-08-29Process for making and using a semiconductor wafer containing first and second does of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-side short configure
#59 | 2017-08-22 ✅ Patent 9,741,703 granted on 2017-08-22Integrated circuit containing standard logic cells and ilbrary-compatible, NCEM-enabled fill cells, including at least via-open-configured, gate-short-configured, TS-short-configured, and AA-short-conigured, NCEM-enabled fill cells
#60 | 2017-08-22 ✅ Patent 9,741,741 granted on 2017-08-22Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATE-short-configured, and GATECNT-short-configured, NCEM-enables fill cells
#61 | 2017-08-08 ✅ Patent 9,728,553 granted on 2017-08-08Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured, NCEM-enabled fill cells
#62 | 2017-08-01 ✅ Patent 9,721,938 granted on 2017-08-01Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including tip-to-tip short configured fill cells, and the second DOE including corner short configured fill cells
#63 | 2017-08-01 ✅ Patent 9,721,937 granted on 2017-08-01Integrated circuit containing first and second does of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-tip short configured fill cells
#64 | 2017-07-18 ✅ Patent 9,711,496 granted on 2017-07-18Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-side short configured fill cells
#65 | 2017-07-18 ✅ Patent 9,711,421 granted on 2017-07-18Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of GATE-snake-open-configured, NCEM-enabled fill cells
#66 | 2017-07-11 ✅ Patent 9,704,846 granted on 2017-07-11IC chips containing a mixture of standard cells obtained from an original set of design rules and enhanced standard cells that are a substantially uniform variant of the original set of design rules and methods for making the same
#67 | 2017-06-27 ✅ Patent 9,691,672 granted on 2017-06-27Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cells
#68 | 2017-06-27 ✅ Patent 9,691,669 granted on 2017-06-27Test structures and methods for measuring silicon thickness in fully depleted silicon-on-insulator technologies
#69 | 2017-06-22 ✅ Patent 9,799,575 granted on 2017-10-24Integrated circuit containing DOEs of NCEM-enabled fill cells
#70 | 2017-05-16 ✅ Patent 9,653,446 granted on 2017-05-16Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, TS-short-configured, and AA-short-configured, NCEM-enabled fill cells
#71 | 2017-05-09 ✅ Patent 9,646,961 granted on 2017-05-09Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, TS-short-configured, and metal-short-configured, NCEM-enabled fill cells
#72 | 2017-04-18 ✅ Patent 9,627,371 granted on 2017-04-18Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and AA-short-configured, NCEM-enabled fill cells
#73 | 2017-04-18 ✅ Patent 9,627,370 granted on 2017-04-18Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cells
#74 | 2017-04-18 ✅ Patent 9,627,408 granted on 2017-04-18D flip-flop cells, with DFM-optimized M0 cuts and V0 adjacencies
#75 | 2017-03-14 ✅ Patent 9,595,536 granted on 2017-03-14Standard cell library that includes 13-CPP and 17-CPP D flip-flop cells, with DFM-optimized M0 cuts and V0 adjacencies
#76 | 2016-12-27 ✅ Patent 9,529,954 granted on 2016-12-27Standard cell library with DFM-optimized M0 cuts
#77 | 2016-11-15 ✅ Patent 9,496,119 granted on 2016-11-15E-beam inspection apparatus and method of using the same on various integrated circuit chips
#78 | 2016-10-04 ✅ Patent 9,461,065 granted on 2016-10-04Standard cell library with DFM-optimized M0 cuts and V0 adjacencies
#79 | 2016-09-06 ✅ Patent 9,438,237 granted on 2016-09-06High-yielding standard cell library and circuits made therefrom
#80 | 2016-04-28 ✅ Patent 9,793,090 granted on 2017-10-17E-beam inspection apparatus and method of using the same on various integrated circuit chips
#81 | 2015-12-01 ✅ Patent 9,202,820 granted on 2015-12-01Flip-flop, latch, and mux cells for use in a standard cell library and integrated circuits made therefrom
#82 | 2013-11-19 ✅ Patent 8,587,341 granted on 2013-11-19Integrated circuit having high pattern regularity
#83 | 2013-11-05 ✅ Patent 8,575,955 granted on 2013-11-05Apparatus and method for electrical detection and localization of shorts in metal interconnect lines
#84 | 2013-07-23 ✅ Patent 8,494,817 granted on 2013-07-23Methods for yield variability benchmarking, assessment, quantification, and localization
#85 | 2013-01-29 ✅ Patent 8,362,480 granted on 2013-01-29Reusable test chip for inline probing of three dimensionally arranged experiments
#86 | 2011-08-23 ✅ Patent 8,004,315 granted on 2011-08-23Process for making and designing an IC with pattern controlled layout regions
#87 | 2011-06-28 ✅ Patent 7,969,199 granted on 2011-06-28Pattern controlled IC layout
#88 | 2011-05-03 ✅ Patent 7,935,965 granted on 2011-05-03Test structures and methods for electrical characterization of alignment of line patterns defined with double patterning
#89 | 2011-02-15 ✅ Patent 7,888,961 granted on 2011-02-15Apparatus and method for electrical detection and localization of shorts in metal interconnect lines
#90 | 2010-11-04 ✅ Patent 8,082,529 granted on 2011-12-20Method and system for mapping a boolean logic network to a limited set of application-domain specific logic cells
#91 | 2010-11-02 ✅ Patent 7,827,516 granted on 2010-11-02Method and system for grouping logic in an integrated circuit design to minimize number of transistors and number of unique geometry patterns
#92 | 2010-01-05 ✅ Patent 7,644,388 granted on 2010-01-05Method for reducing layout printability effects on semiconductor device performance
#93 | 2009-09-22 ✅ Patent 7,592,827 granted on 2009-09-22Apparatus and method for electrical detection and localization of shorts in metal interconnect lines
#94 | 2009-06-04LAYOUT FOR DUT ARRAYS USED IN SEMICONDUCTOR WAFER TESTING
#95 | 2009-02-24 ✅ Patent 7,494,893 granted on 2009-02-24Identifying yield-relevant process parameters in integrated circuit device fabrication processes
#96 | 2009-02-05 ✅ Patent 8,178,876 granted on 2012-05-15Method and configuration for connecting test structures or line arrays for monitoring integrated circuit manufacturing
#97 | 2008-11-13 ✅ Patent 7,673,262 granted on 2010-03-02System and method for product yield prediction
#98 | 2008-10-21 ✅ Patent 7,440,869 granted on 2008-10-21Mapping yield information of semiconductor dice
#99 | 2008-10-07 ✅ Patent 7,434,197 granted on 2008-10-07Method for improving mask layout and fabrication
#100 | 2008-07-17 ✅ Patent 7,807,480 granted on 2010-10-05Test cells for semiconductor yield improvement
Also check out PDF Solutions, Inc.'s (San Jose, United States) applicant profile with 102 patent applications submitted.
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