Scotts Valley, California
United States
29
2013-04-25
21
2016-04-05
These are the the leading inventors for applications assigned to VERTICAL CIRCUITS, INC.:
VERTICAL CIRCUITS, INC. based in Scotts Valley, US has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:
Support mounted electrically interconnected die assembly
#2 | 2012-10-04 ✅ Patent 8,829,677 granted on 2014-09-09Semiconductor die having fine pitch electrical interconnects
#3 | 2012-05-17 ✅ Patent 9,153,517 granted on 2015-10-06Electrical connector between die pad and z-interconnect for stacked die assemblies
#4 | 2011-11-10 ✅ Patent 8,912,661 granted on 2014-12-16Stacked die assembly having reduced stress electrical interconnects
#5 | 2011-11-03 ✅ Patent 9,147,583 granted on 2015-09-29Selective die electrical insulation by additive process
#6 | 2011-06-23 ✅ Patent 8,324,081 granted on 2012-12-04Wafer level surface passivation of stackable integrated circuit chips
#7 | 2011-05-19Flip-chip underfill
#8 | 2011-05-05 ✅ Patent 8,884,403 granted on 2014-11-11Semiconductor die array structure
#9 | 2011-02-17 ✅ Patent 8,629,543 granted on 2014-01-14Electrically interconnected stacked die assemblies
#10 | 2011-01-20 ✅ Patent 8,159,053 granted on 2012-04-17Flat leadless packages and stacked leadless package assemblies
#11 | 2010-12-30 ✅ Patent 8,680,687 granted on 2014-03-25Electrical interconnect for die stacked in zig-zag configuration
#12 | 2010-06-10SEMICONDUCTOR DIE INTERCONNECT FORMED BY AEROSOL APPLICATION OF ELECTRICALLY CONDUCTIVE MATERIAL
#13 | 2010-05-13Sensor
#14 | 2010-03-04Image Sensor
#15 | 2009-12-24 ✅ Patent 7,863,159 granted on 2011-01-04Semiconductor die separation method
#16 | 2009-09-17 ✅ Patent 8,178,978 granted on 2012-05-15Support mounted electrically interconnected die assembly
#17 | 2009-08-20 ✅ Patent 7,843,046 granted on 2010-11-30Flat leadless packages and stacked leadless package assemblies
#18 | 2009-04-23CHIP SCALE STACKED DIE PACKAGE
#19 | 2009-03-12Electrical Interconnect Formed by Pulsed Dispense
#20 | 2008-12-25 ✅ Patent 7,923,349 granted on 2011-04-12Wafer level surface passivation of stackable integrated circuit chips
#21 | 2008-12-25THREE-DIMENSIONAL CIRCUITRY FORMED ON INTEGRATED CIRCUIT DEVICE USING TWO-DIMENSIONAL FABRICATION
#22 | 2008-12-11 ✅ Patent 8,723,332 granted on 2014-05-13Electrically interconnected stacked die assemblies
#23 | 2008-09-18 ✅ Patent 8,742,602 granted on 2014-06-03Vertical electrical interconnect formed on support prior to die mount
#24 | 2007-12-20Three Dimensional Six Surface Conformal Die Coating
#25 | 2007-12-13 ✅ Patent 8,357,999 granted on 2013-01-22Assembly having stacked die mounted on substrate
#26 | 2007-11-01 ✅ Patent 7,535,109 granted on 2009-05-19Die assembly having electrical interconnect
#27 | 2005-11-24 ✅ Patent 7,245,021 granted on 2007-07-17Micropede stacked die component assembly
#28 | 2005-10-20 ✅ Patent 7,215,018 granted on 2007-05-08Stacked die BGA or LGA component assembly
#29 | 2005-10-13 ✅ Patent 7,705,432 granted on 2010-04-27Three dimensional six surface conformal die coating
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