MIPS Technologies, Inc.

User interface for facilitation of high level generation of processor extensions

Apparatus and method for processing template based user defined instructions

Horizontally-shared cache victims in multiple core processors

Apparatus, method and instruction for initiation of concurrent instruction streams in a multithreading microprocessor

Data cache receive flop bypass

Data cache way prediction

Method and apparatus for global ordering to insure latency independent coherence

Apparatus and method for condensing trace information in a multi-processor system

Efficient, scalable and high performance mechanism for handling IO requests

Substituting portion of template instruction parameter with selected virtual instruction parameter

Virtual processor based security for on-chip memory, and applications thereof

Apparatus and method for controlling the exclusivity mode of a level-two cache

Configurable prioritization of core generated interrupts

Clock ratio controller for dynamic voltage and frequency scaled digital systems, and applications thereof

Coherent instruction cache utilizing cache-op execution resources

Interrupt and exception handling for multi-streaming digital processors

Hyperjtag system including debug probe, on-chip instrumentation, and protocol

Automated digital circuit design tool that reduces or eliminates adverse timing constraints due to an inherent clock signal skew, and applications thereof

Thread instruction fetch based on prioritized selection from plural round-robin outputs for different thread states

Support for multiple coherence domains

Microprocessor with improved data stream prefetching using multiple transaction look-aside buffers (TLBs)

Method and apparatus for predicting characteristics of incoming data packets to enable speculative processing to reduce processor latency

Background memory manager that determines if data structures fits in memory with memory state transactions map

Power management for system having one or more integrated circuits

Trace control from hardware and software

Method and apparatus for binding shadow registers to vectored interrupts

HyperJTAG system including debug probe, on-chip instrumentation, and protocol

Preventing writeback race in multiple core processors

Avoiding livelock using intervention messages in multiple core processors

Avoiding livelock using a cache manager in multiple core processors

System debug and trace system and method, and applications thereof

Fetch and dispatch disassociation apparatus for multistreaming processors

Protecting trade secrets during the design and configuration of an integrated circuit semiconductor design

System and method for managing the design and configuration of an integrated circuit semiconductor design

Method for latest producer tracking in an out-of-order processor, and applications thereof

Method and apparatus for predicting characteristics of incoming data packets to enable speculative processing to reduce processor latency

Systems and methods for controlling the use of processing algorithms, and applications thereof

Processor with improved accuracy for multiply-add operations

High performance RISC instruction set digital signal processor having circular buffer and looping controls

System, method, and computer program product for conditionally suspending issuing instructions of a thread

Random cache line refill

Method for latest producer tracking in an out-of-order processor, and applications thereof

Horizontally-shared cache victims in multiple core processors

Conditional move instruction formed into one decoded instruction to be graduated and another decoded instruction to be invalidated

Load/store unit for a processor, and applications thereof

Data cache virtual hint way prediction, and applications thereof

Apparatus and method for tracing processor state from multiple clock domains

Transaction selector employing transaction queue group priorities in multi-port switch

Transaction selector employing round-robin apparatus supporting dynamic priorities in multi-port switch

Transaction selector employing barrel-incrementer-based round-robin apparatus supporting dynamic priorities in multi-port switch

Bifurcated transaction selector supporting dynamic priorities in multi-port switch

Processor with improved accuracy for multiply-add operations

Software programmable hardware state machines

System for synchronizing an in-order co-processor with an out-of-order processor using a co-processor interface store data queue

Coprocessor load data queue for interfacing an out-of-order execution unit with an in-order coprocessor

Methods for reducing data cache access power in a processor using way selection bits

Micro tag array having way selection bits for reducing data cache access power

Method and apparatus for improved computer load and store operations

Instruction encoding to indicate whether to store argument registers as static registers and return address in subroutine stack

Full scan solution for latched-based design

Processor having a compare extension of an instruction set architecture

Random slip generator

Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors

Random cache line refill

Apparatus and method for discrete test access control of multiple cores

Fetch and dispatch disassociation apparatus for multi-streaming processors

Context selection and activation mechanism for activating one of a group of inactive contexts in a processor core for servicing interrupts

Alignment and ordering of vector elements for single instruction multiple data processing

Configurable co-processor interface

Multithreaded dynamic voltage-frequency scaling microprocessor

Instruction encoding for system register bit set and clear

System and method for propagating operand availability prediction bits with instructions through a pipeline in an out-of-order processor

Configurable co-processor interface

Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors

Synchronized storage providing multiple synchronization semantics

External trace synchronization via periodic sampling

Trace control from hardware and software

Conditional branch execution in a processor having a data mover engine that associates register addresses with memory addresses

Conditional branch execution in a processor having a write-tie instruction and a data mover engine that associates register addresses with memory addresses

Conditional branch execution in a processor having a read-tie instruction and a data mover engine that associates register addresses with memory addresses

Functional validation of a packet management unit