Saratoga, California
United States
30
2010-04-29
The entities that hold a legal rights for patent applications filed by inventor Nemirovsky Mario:
Mario Nemirovsky from Saratoga, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Context sharing between a streaming processing unit (SPU) and a packet management unit (PMU) in a packet processing environment
#2 | 2010-01-19Method and apparatus for optimizing selection of available contexts for packet processing in multi-stream packet processing
#3 | 2009-12-15Packet processor that generates packet-start offsets to immediately store incoming streamed packets using parallel, staggered round-robin arbitration to interleaved banks of memory
#4 | 2009-08-04Monitoring of shared-resource locks in a multi-processor system with locked-resource bits packed into registers to detect starved threads
#5 | 2009-03-10Background memory manager that determines if data structures fits in memory with memory state transactions map
#6 | 2008-10-30Fetch and dispatch disassociation apparatus for multistreaming processors
#7 | 2007-12-20Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors
#8 | 2007-11-08Fetch and dispatch disassociation apparatus for multi-streaming processors
#9 | 2007-11-01Context selection and activation mechanism for activating one of a group of inactive contexts in a processor core for servicing interrupts
#10 | 2007-08-14Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors
#11 | 2007-06-21Methods and apparatus for improving fetching and dispatch of instructions in multithreaded processors
#12 | 2007-05-17Method and apparatus for overflowing data packets to a software-controlled memory when they do not fit into a hardware-controlled memory
#13 | 2007-03-29EXTENDED INSTRUCTION SET FOR PACKET PROCESSING APPLICATIONS
#14 | 2007-01-16Context selection and activation mechanism for activating one of a group of inactive contexts in a processor core for servicing interrupts
#15 | 2006-11-21Extended instruction set for packet processing applications
#16 | 2006-11-21Fetch and dispatch disassociation apparatus for multistreaming processors
#17 | 2006-10-05Methods and apparatus for managing a buffer of events in the background
#18 | 2006-09-28Method for allocating memory space for limited packet head and/or tail growth
#19 | 2006-09-28Method and apparatus for non-speculative pre-fetch operation in data packet processing
#20 | 2006-07-20Queueing system for processors in packet routing operations
#21 | 2006-07-13Queueing system for processors in packet routing operations
#22 | 2006-07-11Method and apparatus for allocating and de-allocating consecutive blocks of memory in background memo management
#23 | 2006-06-20Method for allocating memory space for limited packet head and/or tail growth
#24 | 2006-06-06Method and apparatus for preventing undesirable packet download with pending read/write operations in data packet processing
#25 | 2006-06-06Queueing system for processors in packet routing operations
#26 | 2006-05-09Method and apparatus for non-speculative pre-fetch operation in data packet processing
#27 | 2006-04-25Clustering stream and/or instruction queues for multi-streaming processors
#28 | 2006-04-25Methods and apparatus for improving fetching and dispatch of instructions in multithreaded processors
#29 | 2006-04-18Methods and apparatus for managing a buffer of events in the background
#30 | 2006-02-16Method and apparatus for overflowing data packets to a software-controlled memory when they do not fit into a hardware-controlled memory
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