Inventor profile of:

Mario D. NEMIROVSKY

City:

Saratoga, California

Country:

United States

Published Applications:

17

Last publication date:

2011-06-23

Top Assignees for applications by Mario D. NEMIROVSKY

The entities that hold a legal rights for patent applications filed by inventor NEMIROVSKY Mario D.:

Recent patent applications by NEMIROVSKY Mario D.

Mario D. NEMIROVSKY from Saratoga, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2011-06-23
US20110154347A1
Physics

Interrupt and exception handling for multi-streaming digital processors

#2 | 2010-08-12
US20100205608A1
Physics

Mechanism for Managing Resource Locking in a Multi-Threaded Environment

#3 | 2009-09-24
US20090241119A1
Physics

Interrupt and exception handling for multi-streaming digital processors

#4 | 2009-05-14
US20090125660A1
Physics

Interrupt and exception handling for multi-streaming digital processors

#5 | 2008-10-30
US20080270757A1
Physics

Fetch and dispatch disassociation apparatus for multistreaming processors

#6 | 2008-04-15
US10254377
-

Multi-threaded packet processing engine for stateful packet processing

#7 | 2008-02-14
US20080040577A1
Physics

Method and apparatus for improved computer load and store operations

#8 | 2007-12-20
US20070294702A1
Physics

Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors

#9 | 2007-11-08
US20070260852A1
Physics

Fetch and dispatch disassociation apparatus for multi-streaming processors

#10 | 2007-11-01
US20070256079A1
Physics

Context selection and activation mechanism for activating one of a group of inactive contexts in a processor core for servicing interrupts

#11 | 2007-06-21
US20070143580A1
Physics

Methods and apparatus for improving fetching and dispatch of instructions in multithreaded processors

#12 | 2007-03-15
US20070061619A1
Physics

Interrupt and exception handling for multi-streaming digital processors

#13 | 2006-09-28
US20060218556A1
Physics

Mechanism for managing resource locking in a multi-threaded environment

#14 | 2006-09-28
US20060215679A1
Electricity

Method for allocating memory space for limited packet head and/or tail growth

#15 | 2006-07-13
US20060153197A1
Physics

Queueing system for processors in packet routing operations

#16 | 2006-03-28
US9312302
-

Interrupt and exception handling for multi-streaming digital processors

#17 | 2005-04-14
US20050081214A1
Physics

Interstream control and communications for multi-streaming digital processors

InventorID:

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