Santa Clara, California
United States
54
2026-01-22
46
2026-05-26
These are the the leading inventors for applications assigned to Intel NDTM US LLC:
Intel NDTM US LLC based in Santa Clara, US has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:
METHOD AND APPARATUS TO MITIGATE WORD LINE STAIRCASE ETCH STOP LAYER THICKNESS VARIATIONS IN 3D NAND DEVICES
#2 | 2024-10-31 ✅ Patent 12,640,209 granted on 2026-05-26MODULATION OF SOURCE VOLTAGE IN NAND-FLASH ARRAY READ
#3 | 2024-10-24 ✅ Patent 12,625,785 granted on 2026-05-12PERSISTENT DATA STRUCTURE TO TRACK AND MANAGE SSD DEFECTS
#4 | 2024-08-29 ✅ Patent 12,254,933 granted on 2025-03-18Smart prologue for nonvolatile memory program operation
#5 | 2024-07-18 ✅ Patent 12,625,180 granted on 2026-05-12IMPROVED DIAGNOSTIC RING OSCILLATOR CIRCUIT FOR DC AND TRANSIENT CHARACTERIZATION
#6 | 2024-04-25 ✅ Patent 12,394,497 granted on 2025-08-19EFFICIENT BITLINE STABILIZATION FOR PROGRAM INHIBIT IN NAND ARRAYS
#7 | 2024-04-25 ✅ Patent 12,467,974 granted on 2025-11-11DIAGNOSTIC RING OSCILLATOR CIRCUIT FOR DC AND TRANSIENT CHARACTERIZATION
#8 | 2024-02-29 ✅ Patent 12,633,359 granted on 2026-05-19FAST AND EFFICIENT VERIFY RECOVERY AND ARRAY DISCHARGE FOR 3D NAND MEMORY ARRAYS
#9 | 2024-01-11 ✅ Patent 12,518,833 granted on 2026-01-06METHOD AND APPARATUS TO REDUCE TIME TO PROGRAM SINGLE LEVEL CELL BLOCKS IN A NON-VOLATILE MEMORY
#10 | 2023-12-07 ✅ Patent 12,094,545 granted on 2024-09-17Techniques for preventing read disturb in NAND memory
#11 | 2023-12-07 ✅ Patent 12,488,817 granted on 2025-12-02ENHANCED IO INTERFACE FOR PLC PROGRAM AND PROGRAM-SUSPEND-RESUME OPERATIONS
#12 | 2023-11-23MULTI-DECK NAND MEMORY WITH HYBRID DECK SLC
#13 | 2023-11-02 ✅ Patent 12,573,454 granted on 2026-03-10POWER EFFICIENT ARRAY DISCHARGE FOR PROGRAM BOOSTING
#14 | 2023-10-05 ✅ Patent 12,230,334 granted on 2025-02-18Dynamic program caching
#15 | 2023-10-05 ✅ Patent 12,542,187 granted on 2026-02-03APPARATUS AND METHOD TO IMPROVE READ WINDOW BUDGET IN A THREE DIMENSIONAL NAND MEMORY
#16 | 2023-10-05 ✅ Patent 12,531,110 granted on 2026-01-20SYNCHRONOUS INDEPENDENT PLANE READ OPERATION
#17 | 2023-09-28INTERFACE FOR DIFFERENT INTERNAL AND EXTERNAL MEMORY IO PATHS
#18 | 2023-08-31THREE-DIMENSIONAL MEMORY WITH SUPER-PILLAR
#19 | 2023-07-20 ✅ Patent 12,432,922 granted on 2025-09-30METHOD AND APPARATUS TO MITIGATE WORD LINE STAIRCASE ETCH STOP LAYER THICKNESS VARIATIONS IN 3D NAND DEVICES
#20 | 2023-07-20 ✅ Patent 12,315,573 granted on 2025-05-27Method and apparatus to reduce power consumption of page buffer circuitry in a non-volatile memory device
#21 | 2023-07-20 ✅ Patent 12,379,989 granted on 2025-08-05ZERO VOLTAGE PROGRAM STATE DETECTION
#22 | 2023-07-20 ✅ Patent 12,468,484 granted on 2025-11-11EXPRESS STATUS OPERATION FOR STORAGE DEVICES WITH INDEPENDENT PLANES AND PLANE GROUPS
#23 | 2023-06-22 ✅ Patent 12,563,725 granted on 2026-02-24PARALLEL STAIRCASE 3D NAND
#24 | 2023-06-15 ✅ Patent 12,360,669 granted on 2025-07-15METHOD AND APPARATUS TO REDUCE MEMORY IN A NAND FLASH DEVICE TO STORE PAGE RELATED INFORMATION
#25 | 2023-05-25 ✅ Patent 12,568,618 granted on 2026-03-03SELECTIVE REMOVAL OF SIDEWALL MATERIAL FOR 3D NAND INTEGRATION
#26 | 2023-05-25 ✅ Patent 12,564,010 granted on 2026-02-24CHUCK WITH NON-FLAT SHAPED SURFACE
#27 | 2023-05-25 ✅ Patent 12,189,955 granted on 2025-01-07Skip program verify for dynamic start voltage sampling
#28 | 2023-05-04 ✅ Patent 12,580,018 granted on 2026-03-17ADDITIONAL SILICIDE LAYER ON TOP OF STAIRCASE FOR 3D NAND WL CONTACT CONNECTION
#29 | 2023-05-04DYNAMIC NEGATIVE CHARGE PUMP FOR NON-VOLATILE MEMORY
#30 | 2023-04-27 ✅ Patent 12,500,122 granted on 2025-12-16INTERDECK LAYERS AND PILLAR ALIGNMENT
#31 | 2023-04-20STATIC VOLTAGE REGULATOR WITH TIME-INTERLEAVED CHARGE PUMP
#32 | 2023-04-20NAND DUTY CYCLE CORRECTION FOR DATA INPUT WRITE PATH
#33 | 2023-03-16 ✅ Patent 12,315,567 granted on 2025-05-27Grouped global wordline driver with shared bias scheme
#34 | 2023-03-09 ✅ Patent 12,520,495 granted on 2026-01-063D NAND WITH IO CONTACTS IN ISOLATION TRENCH
#35 | 2023-03-02 ✅ Patent 12,393,367 granted on 2025-08-19LEAN COMMAND SEQUENCE FOR MULTI-PLANE READ OPERATIONS
#36 | 2022-12-29 ✅ Patent 12,484,225 granted on 2025-11-25METAL HYBRID CHARGE STORAGE STRUCTURE FOR MEMORY
#37 | 2022-12-22 ✅ Patent 12,424,483 granted on 2025-09-233D NAND WITH INTER-WORDLINE AIRGAP
#38 | 2022-12-22 ✅ Patent 12,488,819 granted on 2025-12-02DUMMY WORDLINE CONTACTS TO IMPROVE ETCH MARGIN OF SEMI-ISOLATED WORDLINES IN STAIRCASE STRUCTURES
#39 | 2022-11-24BARRIER AND THIN SPACER FOR 3D-NAND CUA
#40 | 2022-11-17 ✅ Patent 12,322,455 granted on 2025-06-03Program verify process having placement aware pre-program verify (PPV) bucket size modulation
#41 | 2022-11-17 ✅ Patent 12,362,002 granted on 2025-07-15STAGGERED READ RECOVERY FOR IMPROVED READ WINDOW BUDGET IN A THREE DIMENSIONAL (3D) NAND MEMORY ARRAY
#42 | 2022-11-10 ✅ Patent 12,642,128 granted on 2026-05-26THREE-DIMENSIONAL (3D) NAND COMPONENT WITH CONTROL CIRCUITRY ACROSS MULTIPLE WAFERS
#43 | 2022-09-15 ✅ Patent 12,087,365 granted on 2024-09-10Modulation of source voltage in NAND-flash array read
#44 | 2022-09-15 ✅ Patent 12,266,406 granted on 2025-04-01NAND sensing circuit and technique for read-disturb mitigation
#45 | 2022-09-15 ✅ Patent 12,131,785 granted on 2024-10-29Weak erase pulse
#46 | 2022-09-08 ✅ Patent 12,051,469 granted on 2024-07-30Method and apparatus to mitigate hot electron read disturbs in 3D nand devices
#47 | 2022-06-30 ✅ Patent 12,237,023 granted on 2025-02-25Dynamic detection and dynamic adjustment of sub-threshold swing in a memory cell sensing circuit
#48 | 2022-06-02 ✅ Patent 12,394,492 granted on 2025-08-19MEMORY CELL SENSING CIRCUIT WITH ADJUSTED BIAS FROM PRE-BOOST OPERATION
#49 | 2021-12-09 ✅ Patent 12,046,303 granted on 2024-07-23Smart prologue for nonvolatile memory program operation
#50 | 2021-09-30 ✅ Patent 11,923,010 granted on 2024-03-05Flash memory chip that modulates its program step voltage as a function of chip temperature
#51 | 2021-04-22 ✅ Patent 12,362,016 granted on 2025-07-15READ LATENCY REDUCTION FOR PARTIALLY-PROGRAMMED BLOCK OF NON-VOLATILE MEMORY
#52 | 2020-12-17 ✅ Patent 12,461,654 granted on 2025-11-04METHOD OF DETECTING READ HOTNESS AND DEGREE OF RANDOMNESS IN SOLID-STATE DRIVES (SSDS)
#53 | 2020-07-16 ✅ Patent 12,148,802 granted on 2024-11-19Vertical string driver with channel field management structure
#54 | 2020-07-16 ✅ Patent 12,089,412 granted on 2024-09-10Vertical string driver with extended gate junction structure
Also check out Intel NDTM US LLC's (Santa Clara, United States) applicant profile with 71 patent applications submitted.
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