San Jose, California
United States
40
2025-03-20
40
2026-02-17
These are the the leading inventors for applications assigned to ADEIA SEMICONDUCTOR TECHNOLOGIES LLC:
ADEIA SEMICONDUCTOR TECHNOLOGIES LLC based in San Jose, US has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:
WIRE BONDING METHOD AND APPARATUS FOR ELECTROMAGNETIC INTERFERENCE SHIELDING
#2 | 2025-01-23 ✅ Patent 12,381,117 granted on 2025-08-05THROUGH-DIELECTRIC-VIAS (TDVs) FOR 3D INTEGRATED CIRCUITS IN SILICON
#3 | 2025-01-09 ✅ Patent 12,476,212 granted on 2025-11-183D-INTERCONNECT
#4 | 2024-09-19 ✅ Patent 12,564,086 granted on 2026-02-24STRUCTURES FOR LOW TEMPERATURE BONDING USING NANOPARTICLES
#5 | 2024-09-19 ✅ Patent 12,394,728 granted on 2025-08-19REGION SHIELDING WITHIN A PACKAGE OF A MICROELECTRONIC DEVICE
#6 | 2024-08-08 ✅ Patent 12,324,268 granted on 2025-06-03Image sensor device
#7 | 2024-08-08 ✅ Patent 12,170,268 granted on 2024-12-17Embedded metal lines
#8 | 2024-07-25 ✅ Patent 12,283,572 granted on 2025-04-22Symbiotic network on layers
#9 | 2024-05-16 ✅ Patent 12,094,835 granted on 2024-09-17Wire bonding method and apparatus for electromagnetic interference shielding
#10 | 2024-05-02 ✅ Patent 12,288,771 granted on 2025-04-29Apparatus for non-volatile random access memory stacks
#11 | 2024-02-22 ✅ Patent 12,199,082 granted on 2025-01-14Method of direct-bonded optoelectronic devices
#12 | 2024-02-15 ✅ Patent 12,211,821 granted on 2025-01-28Package-on-package assembly with wire bond vias
#13 | 2024-02-08 ✅ Patent 12,255,153 granted on 2025-03-18Wire bond wires for interference shielding
#14 | 2023-11-23 ✅ Patent 12,293,108 granted on 2025-05-063D memory circuit
#15 | 2023-11-16 ✅ Patent 12,255,176 granted on 2025-03-18Scalable architecture for reduced cycles across SOC
#16 | 2023-10-19 ✅ Patent 12,027,487 granted on 2024-07-02Structures for low temperature bonding using nanoparticles
#17 | 2023-10-05 ✅ Patent 12,166,024 granted on 2024-12-10Direct-bonded LED arrays drivers
#18 | 2023-08-24 ✅ Patent 12,237,306 granted on 2025-02-25Correction die for wafer/die stack
#19 | 2023-06-15 ✅ Patent 12,557,615 granted on 2026-02-17METHODS FOR BONDING SEMICONDUCTOR ELEMENTS
#20 | 2023-04-27 ✅ Patent 11,973,056 granted on 2024-04-30Methods for low temperature bonding using nanoparticles
#21 | 2023-04-27 ✅ Patent 12,640,483 granted on 2026-05-26RADIO FREQUENCY DEVICE PACKAGES
#22 | 2023-04-27 ✅ Patent 11,978,724 granted on 2024-05-07Diffused bitline replacement in memory
#23 | 2023-04-06 ✅ Patent 12,191,267 granted on 2025-01-07Nanowire bonding interconnect for fine-pitch microelectronics
#24 | 2023-02-09 ✅ Patent 12,272,673 granted on 2025-04-08Capacitive coupling in a direct-bonded interface for microelectronic devices
#25 | 2023-01-05 ✅ Patent 11,990,382 granted on 2024-05-21Fine pitch BVA using reconstituted wafer with area array accessible for testing
#26 | 2022-10-06 ✅ Patent 11,837,556 granted on 2023-12-05Wire bonding method and apparatus for electromagnetic interference shielding
#27 | 2022-07-07 ✅ Patent 11,929,347 granted on 2024-03-12Mixed exposure for large die
#28 | 2022-04-28 ✅ Patent 12,635,510 granted on 2026-05-19INTERCONNECT STRUCTURES AND METHODS FOR FORMING SAME
#29 | 2022-03-31 ✅ Patent 11,999,001 granted on 2024-06-04Advanced device assembly structures and methods
#30 | 2021-11-25 ✅ Patent 11,935,907 granted on 2024-03-19Image sensor device
#31 | 2021-10-21 ✅ Patent 12,500,209 granted on 2025-12-16EMBEDDED ORGANIC INTERPOSER FOR HIGH BANDWIDTH
#32 | 2021-09-16 ✅ Patent 11,715,730 granted on 2023-08-01Direct-bonded LED arrays including optical elements configured to transmit optical signals from LED elements
#33 | 2021-07-22 ✅ Patent 11,710,718 granted on 2023-07-25Structures and methods for low temperature bonding using nanoparticles
#34 | 2021-06-24 ✅ Patent 11,876,076 granted on 2024-01-16Apparatus for non-volatile random access memory stacks
#35 | 2021-06-17 ✅ Patent 12,124,035 granted on 2024-10-22Stretchable film assembly with conductive traces
#36 | 2021-05-13 ✅ Patent 11,862,602 granted on 2024-01-02Scalable architecture for reduced cycles across SOC
#37 | 2021-04-22 ✅ Patent 12,113,054 granted on 2024-10-08Non-volatile dynamic random access memory
#38 | 2021-04-15 ✅ Patent 11,621,246 granted on 2023-04-04Diffused bitline replacement in stacked wafer memory
#39 | 2021-03-18 ✅ Patent 11,908,739 granted on 2024-02-20Flat metal features for microelectronics applications
#40 | 2016-11-24 ✅ Patent 12,087,629 granted on 2024-09-10Through-dielectric-vias (TDVs) for 3D integrated circuits in silicon
Also check out ADEIA SEMICONDUCTOR TECHNOLOGIES LLC's (San Jose, United States) applicant profile with 74 patent applications submitted.
348426 ⎘