Sunnyvale, California
United States
154
2014-09-18
133
2020-01-21
These are the the leading inventors for applications assigned to MIPS Technologies, Inc.:
MIPS Technologies, Inc. based in Sunnyvale, US has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:
Superforwarding Processor
#2 | 2014-09-11Apparatus and Method for Transitive Instruction Scheduling
#3 | 2014-09-11 ✅ Patent 10,540,179 granted on 2020-01-21Apparatus and method for bonding branch instruction with architectural delay slot
#4 | 2014-09-11Apparatus and Method for Memory Operation Bonding
#5 | 2014-09-11 ✅ Patent 9,189,412 granted on 2015-11-17Apparatus and method for operating a processor with an operation cache
#6 | 2014-09-04Branch Target Buffer With Efficient Return Prediction Capability
#7 | 2014-08-28 ✅ Patent 9,135,067 granted on 2015-09-15Resource sharing using process delay
#8 | 2014-08-28Precision Exception Signaling for Multiple Data Architecture
#9 | 2014-08-28Deferred Saving of Registers in a Shared Register Pool for a Multithreaded Microprocessor
#10 | 2014-08-28 ✅ Patent 9,720,840 granted on 2017-08-01Way lookahead
#11 | 2014-03-06 ✅ Patent 9,223,721 granted on 2015-12-29Embedded processor with virtualized security controls using guest identifications, a common kernel address space and operational permissions
#12 | 2014-01-02 ✅ Patent 9,069,612 granted on 2015-06-30Carry look-ahead adder with generate bits and propagate bits used for column sums
#13 | 2013-12-12 ✅ Patent 10,534,614 granted on 2020-01-14Rescheduling threads using different cores in a multithreaded microprocessor having a shared register pool
#14 | 2013-10-03 ✅ Patent 9,086,906 granted on 2015-07-21Apparatus and method for guest and root register sharing in a virtual machine
#15 | 2013-07-25 ✅ Patent 8,924,454 granted on 2014-12-30Merged floating point operation using a modebit
#16 | 2013-06-20System For Compression Of Fixed Width Values In A Processor Hardware Trace
#17 | 2013-06-20Vector Size Agnostic Single Instruction Multiple Data (SIMD) Processor Architecture
#18 | 2013-06-20System and method for Automatic Hardware Interrupt Handling
#19 | 2013-05-23 ✅ Patent 9,817,433 granted on 2017-11-14Apparatus and method for achieving glitch-free clock domain crossing signals
#20 | 2013-05-23 ✅ Patent 9,235,510 granted on 2016-01-12Processor with kernel mode access to user space virtual addresses
#21 | 2013-03-14Apparatus and Method for Low Overhead Correlation of Multi-Processor Trace Information
#22 | 2013-03-07Systems and Methods for Controlling the Use of Processing Algorithms, and Applications Thereof
#23 | 2013-01-31Support for Multiple Coherence Domains
#24 | 2012-12-27Apparatus and Method for Accelerated Hardware Page Table Walk
#25 | 2012-12-20Programmable Memory Address
#26 | 2012-12-20 ✅ Patent 10,496,461 granted on 2019-12-03Apparatus and method for hardware initiation of emulated instructions
#27 | 2012-11-15Multithreaded Operation of A Microprocessor Cache
#28 | 2012-08-30SOFTWARE PROGRAMMABLE HARDWARE STATE MACHINES
#29 | 2012-04-05Method and Apparatus for Predicting Characteristics of Incoming Data Packets to Enable Speculative Processing to Reduce Processor Latency
#30 | 2012-03-29 ✅ Patent 8,789,042 granted on 2014-07-22Microprocessor system for virtual machine execution
#31 | 2012-03-29 ✅ Patent 8,239,620 granted on 2012-08-07Microprocessor with dual-level address translation
#32 | 2012-02-09 ✅ Patent 8,392,746 granted on 2013-03-05Clock ratio controller for dynamic voltage and frequency scaled digital systems, and applications thereof
#33 | 2012-02-02 ✅ Patent 8,392,644 granted on 2013-03-05System and method for automatic hardware interrupt handling
#34 | 2011-06-23 ✅ Patent 8,234,456 granted on 2012-07-31Apparatus and method for controlling the exclusivity mode of a level-two cache
#35 | 2011-06-09 ✅ Patent 8,291,364 granted on 2012-10-16Automated digital circuit design tool that reduces or eliminates adverse timing constraints do to an inherent clock signal skew, and applications thereof
#36 | 2011-04-28 ✅ Patent 8,209,522 granted on 2012-06-26System and method for extracting fields from packets having fields spread over more than one register
#37 | 2011-03-22 ✅ Patent 7,911,952 granted on 2011-03-22Interface with credit-based flow control and sustained bus signals
#38 | 2011-03-03Alignment and Ordering of Vector Elements for Single Instruction Multiple Data Processing
#39 | 2011-03-03 ✅ Patent 8,725,950 granted on 2014-05-13Horizontally-shared cache victims in multiple core processors
#40 | 2011-02-17 ✅ Patent 8,266,620 granted on 2012-09-11Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts
#41 | 2011-02-17 ✅ Patent 8,078,806 granted on 2011-12-13Microprocessor with improved data stream prefetching
#42 | 2011-01-20 ✅ Patent 8,185,717 granted on 2012-05-22Apparatus and method for profiling software performance on a processor with non-unique virtual addresses
#43 | 2010-12-09Microprocessor with Compact Instruction Set Architecture
#44 | 2010-12-02Processor Core and Method for Managing Program Counter Redirection in an Out-of-Order Processor Pipeline
#45 | 2010-11-11 ✅ Patent 9,274,796 granted on 2016-03-01Variable register and immediate field encoding in an instruction set architecture
#46 | 2010-08-05 ✅ Patent 9,218,183 granted on 2015-12-22System and method for improving memory transfer
#47 | 2010-06-29 ✅ Patent 7,747,989 granted on 2010-06-29Virtual machine coprocessor facilitating dynamic compilation
#48 | 2010-05-06 ✅ Patent 8,151,268 granted on 2012-04-03Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency
#49 | 2010-05-06 ✅ Patent 8,145,884 granted on 2012-03-27Apparatus, method and instruction for initiation of concurrent instruction streams in a multithreading microprocessor
#50 | 2010-05-04 ✅ Patent 7,711,926 granted on 2010-05-04Mapping system and method for instruction set processing
#51 | 2010-05-04 ✅ Patent 7,711,763 granted on 2010-05-04Microprocessor instructions for performing polynomial arithmetic operations
#52 | 2010-04-29 ✅ Patent 8,081,645 granted on 2011-12-20Context sharing between a streaming processing unit (SPU) and a packet management unit (PMU) in a packet processing environment
#53 | 2010-02-25 ✅ Patent 8,327,121 granted on 2012-12-04Data cache receive flop bypass
#54 | 2010-02-25 ✅ Patent 8,392,651 granted on 2013-03-05Data cache way prediction
#55 | 2010-02-04 ✅ Patent 8,190,865 granted on 2012-05-29Instruction encoding for system register bit set and clear
#56 | 2010-01-19 ✅ Patent 7,649,901 granted on 2010-01-19Method and apparatus for optimizing selection of available contexts for packet processing in multi-stream packet processing
#57 | 2010-01-14 ✅ Patent 9,092,343 granted on 2015-07-28Data cache virtual hint way prediction, and applications thereof
#58 | 2010-01-07 ✅ Patent 8,037,253 granted on 2011-10-11Method and apparatus for global ordering to insure latency independent coherence
#59 | 2009-12-31 ✅ Patent 7,925,859 granted on 2011-04-12Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor
#60 | 2009-12-17 ✅ Patent 7,895,423 granted on 2011-02-22Method for extracting fields from packets having fields spread over more than one register
#61 | 2009-12-15 ✅ Patent 7,634,638 granted on 2009-12-15Instruction encoding for system register bit set and clear
#62 | 2009-11-12Microprocessor with Compact Instruction Set Architecture
#63 | 2009-10-01 ✅ Patent 8,230,202 granted on 2012-07-24Apparatus and method for condensing trace information in a multi-processor system
#64 | 2009-10-01 ✅ Patent 8,074,058 granted on 2011-12-06Providing extended precision in SIMD vector arithmetic operations
#65 | 2009-09-24 ✅ Patent 7,926,062 granted on 2011-04-12Interrupt and exception handling for multi-streaming digital processors
#66 | 2009-09-17 ✅ Patent 8,001,283 granted on 2011-08-16Efficient, scalable and high performance mechanism for handling IO requests
#67 | 2009-08-06 ✅ Patent 7,899,993 granted on 2011-03-01Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme
#68 | 2009-07-30 ✅ Patent 8,024,539 granted on 2011-09-20Virtual processor based security for on-chip memory, and applications thereof
#69 | 2009-06-18 ✅ Patent 8,392,663 granted on 2013-03-05Coherent instruction cache utilizing cache-op execution resources
#70 | 2009-05-14 ✅ Patent 7,900,207 granted on 2011-03-01Interrupt and exception handling for multi-streaming digital processors
#71 | 2009-05-07 ✅ Patent 7,925,864 granted on 2011-04-12Method and apparatus for binding shadow registers to vectored interrupts
#72 | 2009-04-30 ✅ Patent 7,917,882 granted on 2011-03-29Automated digital circuit design tool that reduces or eliminates adverse timing constraints due to an inherent clock signal skew, and applications thereof
#73 | 2009-04-30 ✅ Patent 8,078,840 granted on 2011-12-13Thread instruction fetch based on prioritized selection from plural round-robin outputs for different thread states
#74 | 2009-03-26 ✅ Patent 8,131,941 granted on 2012-03-06Support for multiple coherence domains
#75 | 2009-03-19 ✅ Patent 7,822,943 granted on 2010-10-26Microprocessor with improved data stream prefetching using multiple transaction look-aside buffers (TLBs)
#76 | 2009-03-19 ✅ Patent 8,077,734 granted on 2011-12-13Method and apparatus for predicting characteristics of incoming data packets to enable speculative processing to reduce processor latency
#77 | 2009-02-19 ✅ Patent 8,069,354 granted on 2011-11-29Power management for system having one or more integrated circuits
#78 | 2009-02-05 ✅ Patent 7,644,319 granted on 2010-01-05Trace control from hardware and software
#79 | 2008-12-25 ✅ Patent 7,769,957 granted on 2010-08-03Preventing writeback race in multiple core processors
#80 | 2008-12-25 ✅ Patent 7,769,958 granted on 2010-08-03Avoiding livelock using intervention messages in multiple core processors
#81 | 2008-12-25 ✅ Patent 7,739,455 granted on 2010-06-15Avoiding livelock using a cache manager in multiple core processors
#82 | 2008-11-13 ✅ Patent 7,886,150 granted on 2011-02-08System debug and trace system and method, and applications thereof
#83 | 2008-10-30 ✅ Patent 7,636,836 granted on 2009-12-22Fetch and dispatch disassociation apparatus for multistreaming processors
#84 | 2008-09-11 ✅ Patent 7,774,723 granted on 2010-08-10Protecting trade secrets during the design and configuration of an integrated circuit semiconductor design
#85 | 2008-09-11 ✅ Patent 8,103,987 granted on 2012-01-24System and method for managing the design and configuration of an integrated circuit semiconductor design
#86 | 2008-07-31 ✅ Patent 8,024,393 granted on 2011-09-20Processor with improved accuracy for multiply-add operations
#87 | 2008-07-03 ✅ Patent 7,840,874 granted on 2010-11-23Speculative cache tag evaluation
#88 | 2008-07-03 ✅ Patent 7,865,647 granted on 2011-01-04Efficient resource arbitration
#89 | 2008-06-12 ✅ Patent 7,676,660 granted on 2010-03-09System, method, and computer program product for conditionally suspending issuing instructions of a thread
#90 | 2008-06-05 ✅ Patent 8,190,665 granted on 2012-05-29Random cache line refill
#91 | 2008-04-17 ✅ Patent 7,774,549 granted on 2010-08-10Horizontally-shared cache victims in multiple core processors
#92 | 2008-04-03 ✅ Patent 8,078,846 granted on 2011-12-13Conditional move instruction formed into one decoded instruction to be graduated and another decoded instruction to be invalidated
#93 | 2008-04-03 ✅ Patent 7,594,079 granted on 2009-09-22Data cache virtual hint way prediction, and applications thereof
#94 | 2008-03-20 ✅ Patent 7,773,621 granted on 2010-08-10Transaction selector employing round-robin apparatus supporting dynamic priorities in multi-port switch
#95 | 2008-03-20 ✅ Patent 7,760,748 granted on 2010-07-20Transaction selector employing barrel-incrementer-based round-robin apparatus supporting dynamic priorities in multi-port switch
#96 | 2008-03-20 ✅ Patent 7,961,745 granted on 2011-06-14Bifurcated transaction selector supporting dynamic priorities in multi-port switch
#97 | 2008-03-13 ✅ Patent 8,151,093 granted on 2012-04-03Software programmable hardware state machines
#98 | 2008-03-06 ✅ Patent 8,032,734 granted on 2011-10-04Coprocessor load data queue for interfacing an out-of-order execution unit with an in-order coprocessor
#99 | 2008-02-21 ✅ Patent 7,657,708 granted on 2010-02-02Methods for reducing data cache access power in a processor using way selection bits
#100 | 2008-02-21 ✅ Patent 7,650,465 granted on 2010-01-19Micro tag array having way selection bits for reducing data cache access power
Also check out MIPS Technologies, Inc.'s (Sunnyvale, United States) applicant profile with 3 patent applications submitted.
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