171775 ⎘
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere; Testing of electronic circuits, e.g. by signal tracer; Testing of integrated circuits [IC] Environmental, reliability or burn-in testing
Sub-classes:TEST DEVICE
#2SYSTEMS, APPARATUSES, AND METHODS FOR TESTING, ANALYZING, AND ASSEMBLING RF MODULES
#3SYSTEMS AND METHODS FOR IDENTIFYING INTEGRATED CIRCUIT HARDWARE BASED ON SCAN-BASED FEATURE IDENTIFIERS
#4METHOD OF TESTING AN INTEGRATED CIRCUIT AND TESTING SYSTEM
#5SYSTEM FOR TESTING AN INTEGRATED CIRCUIT OF A DEVICE AND ITS METHOD OF USE
#6Controlling alignment during a thermal cycle
#7PROTECTING METHOD FOR PREVENTING SOLDER CRACK FAILURE IN ELECTRONIC PRODUCT
#8Apparatus for testing electronic devices
#9METHOD OF TESTING AN INTEGRATED CIRCUIT AND TESTING SYSTEM
#10Semiconductor Wafer
#11System for testing an integrated circuit of a device and its method of use
#12SYSTEM AND METHODS FOR ANALYZING AND ESTIMATING SUSCEPTIBILITY OF CIRCUITS TO RADIATION-INDUCED SINGLE-EVENT-EFFECTS
#13Method of testing an integrated circuit and testing system
#14Chip, self-calibration circuit and method for chip parameter offset upon power-up
#15JTAG-based burning device
#16Semiconductor chip burn-in test with mutli-channel
#17Apparatus for testing electronic devices
#18Pressure relief valve
#19System and methods for analyzing and estimating susceptibility of circuits to radiation-induced single-event-effects
#20Semiconductor device and burn-in test method thereof
#21Apparatus for testing electronic devices
#22Method for the characterization and monitoring of integrated circuits
#23Pressure relief valve
#24System and methods for analyzing and estimating susceptibility of circuits to radiation-induced single-event-effects
#25Method for the characterization and monitoring of integrated circuits
#26IC degradation management circuit, system and method
#27Semiconductor device structures for burn-in testing and methods thereof
#28Burn-in system energy management
#29Semiconductor device structures for burn-in testing and methods thereof
#30Apparatus for testing electronic devices
#31System and methods for analyzing and estimating susceptibility of circuits to radiation-induced single-event-effects
#32Systems and methods for improved delamination characteristics in a semiconductor package
#33Voltage regulator having an overheat detection circuit and test terminal
#34RELIABILITY MANAGEMENT SYSTEM AND OPERATION THEREOF
#35Manufacturing method and program of semiconductor device
#36Integrated circuit reliability assessment apparatus and method
#37Limiting translation for consistent substrate-to-substrate contact
#38System and methods for analyzing and estimating susceptibility of circuits to radiation-induced single-event-effects
#39Driving circuit of display panel and the quality test method thereof
#40System and methods for analyzing and estimating susceptibility of circuits to radiation-induced single-event-effects
#41IC degradation management circuit, system and method
#42Testing electronic devices
#43Massively parallel wafer-level reliability system and process for massively parallel wafer-level reliability testing
#44Screening method for electrolytic capacitors
#45Method for the characterization and monitoring of integrated circuits
#46Integrated time dependent dielectric breakdown reliability testing
#47Method for the characterization and monitoring of integrated circuits
#48Apparatus for testing electronic devices
#49IC with insulating trench and related methods
#50Integrated circuit device comprising environment-hardened die and less-environment-hardened die
#51Devices under test
#52Method for manufacturing silicon carbide semiconductor apparatus, and energization test apparatus
#53Manufacturing method and program of semiconductor device
#54Method for the characterization and monitoring of integrated circuits
#55CONFORMAL ELECTRONICS WITH DEFORMATION INDICATORS
#56Overheat protection circuit and method in an accelerated aging test of an integrated circuit
#57METHOD AND EQUIPMENT FOR TESTING SEMICONDUCTOR APPARATUSES SIMULTANEOUSLY AND CONTINUOUSLY
#58Use of a (Digital) PUF for Implementing Physical Degradation/Tamper Recognition for a Digital IC
#59Controlling alignment during a thermal cycle
#60Overclocking as a Method for Determining Age in Microelectronics for Counterfeit Device Screening
#61Method for Temporary Electrical Contacting of a Component Arrangement and Apparatus Therefor
#62Method for verifying a test substrate in a prober under defined thermal conditions
#63Apparatus for testing electronic devices
#64VERIFICATION OF TEST PROGRAM STABILITY AND WAFER FABRICATION PROCESS SENSITIVITY
#65Integrated time dependent dielectric breakdown reliability testing
#66System and process for accounting for aging effects in a computing device
#67Screening method for electrolytic capacitors
#68Method and apparatus for detecting relationship between thermal and electrical properties of semiconductor device
#69Reliability test screen optimization
#70Integrated time dependent dielectric breakdown reliability testing
#71Selective solder bump formation on wafer
#72Method and equipment for testing semiconductor apparatuses simultaneously and continuously
#73Method for estimating the lifespan of a deep-sub-micron integrated electronic circuit
#74Method and apparatus for multi-planar edge-extended wafer translator
#75Apparatus for testing electronic devices
#76System for testing an integrated circuit of a device and its method of use
#77Method for verifying a test substrate in a prober under defined thermal conditions
#78Method and system for assessing reliability of integrated circuit
#79Probing structure for evaluation of slow slew-rate square wave signals in low power circuits
#80Testing method for a semiconductor integrated circuit device, semiconductor integrated circuit device and testing system
#81Burn-in method for surface emitting semiconductor laser device
#82System for testing an integrated circuit of a device and its method of use
#83Apparatus for testing electronic devices
#84Method and Apparatus For Multi-Planar Edge-Extended Wafer Translator
#85Method of detecting abnormality in burn-in apparatus
#86USING MULTIVARIATE HEALTH METRICS TO DETERMINE MARKET SEGMENT AND TESTING REQUIREMENTS
#87Technique for aging induced performance drift compensation in an integrated circuit
#88Packaging reliability superchips
#89Semiconductor Integrated Circuit Device, Method For Testing The Semiconductor Integrated Circuit Device, Semiconductor Wafer And Burn-In Test Apparatus
#90Probe station thermal chuck with shielding for capacitive current
#91Apparatus for fixed-form multi-planar extension of electrical conductors beyond the margins of a substrate
#92Universal wafer carrier for wafer level die burn-in
#93Self-testing apparatus with controllable environmental stress screening (ESS)
#94Probe station thermal chuck with shielding for capacitive current
#95Apparatus for testing electronic devices
#96Packaging reliability super chips
#97Efficient air-flow loop through dual burn-in chambers with removable pattern-generator boards for memory-module environmental testing
#98Wafer burn-in and text employing detachable cartridge
#99Semiconductor wafer and testing method therefor
#100System and method for burn-in test control
#101Method for testing using a universal wafer carrier for wafer level die burn-in
#102Method for testing using a universal wafer carrier for wafer level die burn-in
#103Method for testing using a universal wafer carrier for wafer level die burn-in
#104Method for testing using a universal wafer carrier for wafer level die burn-in
#105Method for testing using a universal wafer carrier for wafer level die burn-in
#106System and method for measuring time dependent dielectric breakdown with a ring oscillator
#107System and method for measuring negative bias thermal instability with a ring oscillator
#108Circuitry and methodology to establish correlation between gate dielectric test site reliability and product gate reliability
#109Methods, apparatus and systems for wafer-level burn-in stressing of semiconductor devices
#110Manifold-Distributed Air Flow Over Removable Test Boards in a Memory-Module Burn-In System With Heat Chamber Isolated by Backplane
#111Device for generating internal voltages in burn-in test mode
#112Systems, apparatuses, and methods for testing, analyzing, and assembling RF modules
#113Systems, apparatuses, and methods for testing, analyzing, and assembling RF modules
#114Assessment of HCI in logic circuits based on AC stress in discrete FETs
#115Controlled impedance charged device tester
#116Power measurement transducer