171836 ⎘
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere; Testing of electronic circuits, e.g. by signal tracer; Testing of digital circuits; Input or output aspects Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
PROBE DEVICE AND TEST DEVICE INCLUDING THE SAME
#2TEMPORAL LOCKSTEP
#3TEMPORAL LOCKSTEP
#4METHOD AND APPARATUS FOR FAULT DETECTING OF INVERTER
#5ANALYZING TRANSMISSION LINES
#6TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENT
#7Secured scan access for a device including a scan chain
#8CAN TRANSCEIVER AND METHOD FOR THE CAN TRANSCEIVER
#9SECURED SCAN ACCESS FOR A DEVICE INCLUDING A SCAN CHAIN
#10Adaptive port ceiling assignment for background I/O operations between heterogeneous storage arrays
#11Wafer level methods of testing semiconductor devices using internally-generated test enable signals
#12Pin Testing System for Multi-Pin Chip and Method Thereof
#13Built-in self-test for die-to-die physical interfaces
#14Fan-out buffer with skew control function, operating method thereof, and probe card including the same
#15Test compression in a JTAG daisy-chain environment
#16TEST AND DEBUG SUPPORT WITH HBI CHIPLET ARCHITECTURE
#17Integrated circuit including test circuit and method of manufacturing the same
#18Built-in self-test for die-to-die physical interfaces
#19Wafer level methods of testing semiconductor devices using internally-generated test enable signals
#20Signal test
#21System and method of testing single DUT through multiple cores in parallel
#22Telephone connector to audio connector mapping and leveling device
#23Method and/or system for testing devices in non-secured environment
#24INPUT-OUTPUT DEVICE WITH DEBUG CONTROLLER
#25Margin test data tagging and predictive expected margins
#26Device, system and method to support communication of test, debug or trace information with an external input/output interface
#27Digital Input and Output Signal Test Platform
#28Test compression in a JTAG daisy-chain environment
#29Method of high speed and dynamic configuration of a transceiver system
#30Testing of asynchronous reset logic
#31Methods and apparatuses to detect test probe contact at external terminals
#32Wafer level methods of testing semiconductor devices using internally-generated test enable signals
#33Device, system and method to support communication of test, debug or trace information with an external input/output interface
#34Systems, methods and devices for high-speed input/output margin testing
#35Systems, methods and devices for high-speed input/output margin testing
#36Drive circuit and liquid ejecting apparatus
#37Time interleaved scan system
#38Test compression in a JTAG daisy-chain environment
#39Device and method for testing a computer system
#40Core testing machine
#41Telephone connector to audio connector mapping and leveling device
#42Memory loopback systems and methods
#43Device, system and method to support communication of test, debug or trace information with an external input/output interface
#44First tap, test compression architecture; second tap, test compression architecture
#45Method for identifying a fault at a device output and system therefor
#46Memory loopback systems and methods
#47Method and system of determining application health in an information technology environment
#48In-field system test security
#49In-field system testing
#50Semiconductor device and semiconductor system
#51Apparatus for adding jitters to the edges of a pulse sequence
#52Interface independent test boot method and apparatus using automatic test equipment
#53Automatic device detection and connection verification
#54Test compression in a JTAG daisy-chain environment
#55Detection circuits, detection method, and electronic systems for I/O output status
#56Platform component interconnect testing
#57Adapting the usage configuration of integrated circuit input-output pads
#58Integrated circuit die having a split solder pad
#59Core testing machine
#60Multi-channel fault detection with a single diagnosis output
#61Method for testing through silicon vias in 3D integrated circuits
#62On-die measurement technique for I/O DC parameters Vand V
#63Device, system and method to support communication of test, debug or trace information with an external input/output interface
#64Core testing machine
#65Semiconductor device and semiconductor system
#66TDI, SC, and SE gating circuitry with count complete input
#67Test devices and test systems
#68Semiconductor devices and semiconductor systems including the same
#69Semiconductor device and method of testing semiconductor device
#70SEMICONDUCTOR PACKAGE
#71Duty cycle based timing margining for I/O AC timing
#72Input/output cell, integrated circuit device and methods of providing on-chip test functionality
#73Testing I/O timing defects for high pin count, non-contact interfaces
#74Integrated circuit testing interface on automatic test equipment
#75Field triage of EOS failures in semiconductor devices
#76Parallel scan distributors and collectors and process of testing integrated circuits
#77Signal processing system with BIST function, testing method thereof and testing signal generator
#78IO pad circuitry with safety monitoring and control for integrated circuits
#79Testing integrated circuit packaging for output short circuit current
#80Parallel scan paths with three bond pads, distributors and collectors
#81Semiconductor device which can detect abnormality
#82Systems and methods for testing electronic devices that include low power output drivers
#83Self-test design for serializer / deserializer testing
#84Probeless testing of pad buffers on wafer
#85Method for detecting working state of I/O pins of electronic components using charges from human body
#86Data receiver device and test method thereof
#87Communication system, data transmitter, and data receiver capable of detecting incorrect receipt of data
#88TEST INTERFACE CIRCUIT FOR INCREASING TESTING SPEED
#89Gating of clock-DR and pause-DR from TAP to TCA
#90Core circuitry, input and output buffers, and four bypass switches
#91Electrical characterization for a semiconductor device pin
#92Parallel scan paths with three bond pads, distributors and collectors
#93Pad switch cells selectively coupling test leads to test pads
#94System for performing electrical characterization of asynchronous integrated circuit interfaces
#95Method of manufacturing non-volatile memory module
#96Scan path switch testing of output buffer with ESD
#97System and method for packet communication
#98IR gating SC signals during TAP Clock-DR and Pause-DR states
#99Latching control buffer between functional logic and tri-state output buffer
#100Test chain testability in a system for testing tri-state functionality
#101Semiconductor device
#102Output buffer with process and temperature compensation
#103Logic applying serial test bits to scan paths in parallel
#104Methods for defect testing of externally accessible integrated circuit interconnects
#105SEMICONDUCTOR INTEGRATED CIRCUIT AND ELECTRONIC INFORMATION DEVICE
#106Electrical interconnection integrated device with fault detecting module and electronic apparatus comprising the device
#107IC OUTPUT SIGNAL PATH WITH SWITCH, BUS HOLDER, AND BUFFER
#108Input buffer, test switches and switch control with serial I/O
#109Test circuit for serial link receiver
#110Protocol sequence generator
#111SYSTEM, METHOD, AND APPARATUS FOR PROVIDING REDUNDANT POWER CONTROL USING A DIGITAL OUTPUT MODULE
#112Integrated circuit die, an integrated circuit package and a method for connecting an integrated circuit die to an external device
#113SEMICONDUCTOR DEVICE
#114IC with first and second distributors collectors and scan paths
#115Method and device for multi-dimensional processing using a single-state decision feedback equalizer
#116METHOD FOR TESTING SEMICONDUCTOR MEMORY DEVICE USING PROBE AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME
#117Logic applying different bit positions to respective scan paths
#118Multi-pair gigabit ethernet transceiver
#119Method and system for testing chips
#120IC output signal path with switch, bus holder, and buffer
#121PHY control module for a multi-pair gigabit transceiver
#122TESTABLE CIRCUIT WITH INPUT/OUTPUT CELL FOR STANDARD CELL LIBRARY
#123Selective core functional and bypass circuitry
#124Tap control of TCA scan clock and scan enable
#125Multi-pair gigabit ethernet transceiver having adaptive disabling of circuit elements
#126I/O switches and serializer for each parallel scan register
#127Communication system, data transmitter, and data receiver capable of detecting incorrect receipt of data
#128TESTABLE INTEGRATED CIRCUIT AND IC TEST METHOD
#129System and method for high-speed decoding and ISI compensation in a multi-pair transceiver system
#130Transfer circuit, transmitter, receiver and test apparatus
#131Test circuit and test method for testing differential input circuit
#132Semiconductor device
#133TESTABLE INTEGRATED CIRCUIT AND TEST METHOD
#134IC output signal path with switch, bus holder, and buffer
#135Method and apparatus for testing an electronic circuit integrated with a semiconductor device
#136Tester, method for testing a device under test and computer program
#137Probing analog signals
#138Integrated circuit with improved test capability via reduced pin count
#139Demodulator for a multi-pair gigabit transceiver
#140DYNAMIC REGULATION OF POWER CONSUMPTION OF A HIGH-SPEED COMMUNICATION SYSTEM
#141Parallel scan distributors and collectors and process of testing integrated circuits
#142Parallel scan distributors and collectors and process of testing integrated circuits
#143Parallel scan distributors and collectors and process of testing integrated circuits
#144Parallel scan distributors and collectors and process of testing integrated circuits
#145High-speed decoder for a multi-pair gigabit transceiver
#146Physical coding sublayer for a multi-pair gigabit transceiver
#147Systems and methods for defect testing of externally accessible integrated circuit interconnects
#148PORT SELECTOR, DEVICE TESTING SYSTEM AND METHOD USING THE SAME
#149Multi-pair gigabit Ethernet transceiver
#150Integrated circuit communication self-testing
#151Programmable duty cycle distortion generation circuit
#152Scan circuitry controlled switch connecting buffer output to test lead
#153Semiconductor device having user field and vendor field
#154Identification of board connections for differential receivers
#155Circuit testing apparatus
#156Controller applying stimulus data while continuously receiving serial stimulus data
#157Multi-pair gigabit ethernet transceiver
#158Test circuit for a semiconductor integrated circuit
#159Method and system for yield enhancement
#160IC output signal path with switch, bus holder, and buffer
#161Built in self test for input/output characterization
#162Semiconductor device with a plurality of ground planes
#163Method of inspecting semiconductor circuit having logic circuit as inspection circuit
#164Apparatus and method for testing a wireless transceiver
#165Flexible on chip testing circuit for I/O's characterization
#166System and method for high-speed decoding and ISI compensation in a multi-pair transceiver system
#167Parallel scan distributors and collectors and process of testing integrated circuits
#168Parallel scan distributors and collectors and process of testing integrated circuits
#169Parallel scan distributors and collectors and process of testing integrated circuits
#170PHY control module for a multi-pair gigabit transceiver
#171System and method for trellis decoding in a multi-pair transceiver system
#172Three boundary scan cell switches controlling input to output buffer
#173Method, system and apparatus for quantifying the contribution of inter-symbol interference jitter on timing skew budget
#174Test circuit and test method
#175Probeless testing of pad buffers on wafer
#176Input/output circuit for evaluating delay
#177Method of increasing path coverage in transition test generation
#178FLEXIBLE ON CHIP TESTING CIRCUIT FOR I/O'S CHARACTERIZATION
#179FAULT TOLERANT SELECTION OF DIE ON WAFER
#180Systems and methods for defect testing of externally accessible integrated circuit interconnects
#181Dynamic regulation of power consumption of a high-speed communication system
#182Test circuit for serial link receiver
#183Method for testing semiconductor memory device using probe and semiconductor memory device using the same
#184Multi-pair gigabit ethernet transceiver
#185I/O port tester
#186Scan distributor loading scan paths simultaneous with loading test data
#187Pad unit having a test logic circuit and method of driving a system including the same
#188Method and system for testing chips
#189Glitchless clock multiplexer controlled by an asynchronous select signal
#190Semiconductor memory device for adjusting impedance of data output driver
#191Method for verifying interconnected blocks of IP
#192Second state machine active in first state machine SHIFT-DR state
#193Signal output circuit, and test apparatus
#194Multi-pair gigabit ethernet transceiver
#195Integrated circuit
#196Method for at speed testing of devices
#197Isolated conductive leads extending across to opposite sides of IC
#198Semiconductor device
#199IC selectively connecting logic and bypass conductors between opposing pads
#200Characterizing jitter sensitivity of a serializer/deserializer circuit
#201Parametric measurement of high-speed I/O systems
#202Driver IC and inspection method for driver IC and output device
#203Parallel scan distributors and collectors and process of testing integrated circuits
#204Semiconductor integrated circuit device and method of testing the same
#205Multi-pair gigabit ethernet transceiver having a single-state decision feedback equalizer
#206Integrated circuit with improved test capability via reduced pin count
#207Input/output buffer test circuitry and leads additional to boundary scan
#208Split clock scan flip-flop
#209Two boundary scan cell switches controlling input to output buffer
#210Multi-pair gigabit ethernet transceiver having decision feedback equalizer
#211Multi-pair gigabit Ethernet transceiver having adaptive disabling of circuit elements
#212Timing recovery system for a multi-pair gigabit transceiver
#213Providing precise timing control between multiple standardized test instrumentation chassis
#214USB port tester
#215Test device for on die termination
#216Semiconductor memory device for adjusting impedance of data output driver
#217PLL with programmable jitter for loopback serdes testing and the like
#218Testing circuit for a data interface
#219System and method for testing a serial port
#220Method and apparatus for die testing on wafer
#221Semiconductor device
#222Serializer/deserializer circuit for jitter sensitivity characterization
#223Two-bit offset cancelling A/D converter with improved common mode rejection and threshold sensitivity
#224Input-output device testing
#225Method and apparatus for testing an integrated device's input/output (I/O)
#226Method and an apparatus for measuring the input threshold level of device under test
#227Providing precise timing control within a standardized test instrumentation chassis
#228Jitter producing circuitry and methods
#229Jitter producing circuitry and methods
#230Pseudo asynchronous serializer deserializer (SERDES) testing
#231IC input memory with dual data and dual control inputs
#232Semiconductor chip and semiconductor integrated circuit device for relaying a reference clock from one hard macro to another
#233Semiconductor integrated circuit and device and method for testing the circuit
#234Method and apparatus for processor emulation
#235Selective test point for high speed SERDES cores in semiconductor design
#236Jitter producing circuitry and methods
#237Semiconductor device with test circuit and test method of the same
#238Parallel input/output self-test circuit and method
#239High-speed decoder for a multi-pair gigabit transceiver
#240Built-in self-testing of multilevel signal interfaces
#241Method and circuit for parametric testing of integrated circuits with an exclusive-or logic tree
#242Method for the diagnosis of driver outputs and diagnosis pulse manager
#243Analog-differential-circuit test device
#244Built-in test circuit for an integrated circuit device
#245Method to eliminate PLL lock-up during power up for high frequency synthesizer
#246Automatic mode setting and power ramp compensator for system power on conditions
#247Two-bit offset cancelling A/D converter with improved common mode rejection and threshold sensitivity
#248Automatic gain control and tuned low noise amplifier for process-independent gain systems
#249Transfer base substrate and method of semiconductor device
#250Method and apparatus for measuring the input frequency response of a digital receiver
#251System and method for high-speed decoding and ISI compensation in a multi-pair transceiver system
#252Dynamic register with IDDQ testing capability
#253Method for automated at-speed testing of high serial pin count multiple gigabit per second devices
#254First and second scan distributors, collectors, controllers, and multiplexers
#255Universal binding post
#256Single chip device, and method and system for testing the same
#257Selecting groups of dies for wafer testing
#258Semiconductor integrated circuit device
#259Built-in self test technique for programmable impedance drivers for RapidChip and ASIC drivers
#260Testing of integrated circuit receivers
#261System and method for testing input and output characterization on an integrated circuit device
#262PHY control module for a multi-pair gigabit transceiver
#263Circuit and method for evaluating the performance of an adaptive decision feedback equalizer-based serializer deserializer and serdes incorporating the same
#264Semiconductor device with a plurality of ground planes
#265Self-testing input/output pad
#266Built-in self test method and apparatus for jitter transfer, jitter tolerance, and FIFO data buffer
#267Simultaneous switch test mode
#268Driver IC and inspection method for driver IC and output device
#269Method, system and apparatus for quantifying the contribution of inter-symbol interference jitter on timing skew budget
#270Physical coding sublayer for a multi-pair gigabit transceiver
#271Input/output switching arrangement for semiconductor circuits, a method for testing driver circuits in semiconductor circuits
#272Process and device for testing a serializer circuit arrangement and process and device for testing a deserializer circuit arrangement
#273Method and device for monitoring an integrated circuit
#274Apparatus for jitter testing an IC
#275Pair-swap independent trellis decoder for a multi-pair gigabit transceiver
#276Method for training a transceiver for high speed communications
#277Method and apparatus for implementing redundancy enhanced differential signal interface
#278Programmable jitter generator
#279PHY control module for a multi-pair gigabit transceiver
#280Ethernet transceiver with single-state decision feedback equalizer
#281Integrated circuit with test pad structure and method of testing
#282Dynamic regulation of power consumption of a high-speed communication system
#283Dynamic register with IDDQ testing capability
#284Self-test for receive and transmit hardware functional safety associated with a touch panel or screen
#285Temporal lockstep
#286Methods and systems for switchable logic to recover integrated circuits with short circuits
#287Receiving circuit
#288System and method for jitter negation in a high speed serial interface
#289Method for testing through silicon vias in 3D integrated circuits