Machine Learning for Syncing Multiple FPGA Ports in a Quantum System

FAULT DETECTION CIRCUIT

FLEXIBLE TEST INSTRUCTION SET ARCHITECTURE

FAULT DETECTION CIRCUIT

FUNCTIONAL TESTING DEVICE

SCAN TEST IN A SINGLE-WIRE BUS CIRCUIT

REDUNDANT ANALOG BUILT-IN SELF TEST

SYSTEM, METHOD FOR CIRCUIT VALIDATION, AND SYSTEM AND METHOD FOR FACILITATING CIRCUIT VALIDATION

Built-in self-test for die-to-die physical interfaces

TECHNIQUES TO PERFORM SEMICONDUCTOR TESTING

Machine learning for syncing multiple FPGA ports in a quantum system

Redundant analog built-in self test

SYSTEM AND METHOD OF MONITORING PERFORMANCE OF AN ELECTRONIC DEVICE

Scan test in a single-wire bus circuit

Test circuit using clock gating scheme to hold capture procedure and bypass mode, and integrated circuit including the same

INTEGRATED CIRCUIT AND AN ELECTRONIC DEVICE INCLUDING INTEGRATED CIRCUIT

Reduced signaling interface method and apparatus

Built-in self-test for die-to-die physical interfaces

Support device, design support system, electrical device, and design support method

Implementing a JTAG device chain in multi-die integrated circuit

Encoding test data of microelectronic devices, and related methods, devices, and systems

Device for detecting margin of circuit operating at certain speed

System and method for testing critical components on system-on-chip

Scan output flip-flop with power saving feature

Integrated circuit with reduced signaling interface

Applications of adaptive microelectronic circuits that are designed for testability

Implementing a JTAG device chain in multi-die integrated circuit

Display panel test circuit

Automated hardware for input/output (I/O) test regression apparatus

System-on-chip for AT-SPEED test of logic circuit and operating method thereof

Chip and testing method thereof

Automated test equipment for testing one or more devices under test, method for automated testing of one or more devices under test, and computer program for handling command errors

Reduced signaling interface circuit

Automated test equipment for testing one or more devices under test, method for automated testing of one or more devices under test, and computer program using a buffer memory

Automated test equipment using an on-chip-system test controller

Method and an apparatus for reducing the effect of local process variations of a digital circuit on a hardware performance monitor

Method and a circuit for adaptive regulation of body bias voltages controlling NMOS and PMOS transistors of an IC

DISPLAY PANEL AND DISPLAY DEVICE

System-on-chip for at-speed test of logic circuit and operating method thereof

Method for characterization of standard cells with adaptive body biasing

Apparatus and method for generation and adaptive regulation of control voltages in integrated circuits with body biasing or back-biasing

Inter-domain power element testing using scan

Safety circuit and method for testing a safety circuit in an automation system

Real-time oscilloscope with a built-in time domain reflectometry (TDR) and/or time-domain transmission (TDT) function

System and method for providing automation of microprocessor analog input stimulation

Entering home state after soft reset signal after address match

Sleek serial interface for a wrapper boundary register (device and method)

Inspection device

Method for testing an electronic device and an interface circuit therefore

Reconfigurable scan network defect diagnosis

Circuit assembly and method for monitoring a micro-controller based on a watchdog voltage

Configurable probe blocks for system monitoring

OVERRIDING A SIGNAL IN A SEMICONDUCTOR CHIP

Inspection circuit, semiconductor storage element, semiconductor device, and connection inspection method

Method and diagnostic apparatus for performing diagnostic operations upon a target apparatus using transferred state and emulated operation of a transaction master

Address/instruction registers, target domain interfaces, control information controlling all domains

I/O control circuit for reduced pin count (RPC) device testing

System and method for providing temporal visualization of signal relationships in a coherent time-domain ATE test execution environment

Bidirectional scan chain structure and method

Configurable hardware platform for measurement or control

Sleek serial interface for a wrapper boundary register (device and method)

Addressable tap domain selection circuit with instruction and linking circuits

Backplane testing system

LOGIC VERIFICATION APPARATUS, LOGIC VERIFICATION METHOD AND TEST PROGRAM

Backplane testing system

Configurable probe blocks for system monitoring

Scan flip-flop and associated method

Controlling a test run on a device under test without controlling the test equipment testing the device under test

Controlling a test run on a device under test without directly controlling the test equipment within a vendor test platform testing the device under test

Semiconductor devices and semiconductor systems including the same

TEST CIRCUIT DESIGN APPARATUS, TEST CIRCUIT DESIGN PROGRAM, AND TEST CIRCUIT

TAP addressable circuit with bi-directional TMS and second signal lead

On-die signal measurement circuit and method

Monitoring microprocessor interface information for a preset service using an address based filter

Computer-implemented method for real-time testing of a control unit

Linking circuitry selectively coupling TDI/TDO with first and second domains

Digital test system

SEMICONDUCTOR APPARATUS AND TEST METHOD THEREOF

Circuit test system electric element memory control chip under different test modes

Delay fault testing for chip I/O

Address and instruction controller with TCK, TMS, address match inputs

Method for characterizing integrated circuits for identification or security purposes

Inverter and TMS clocked flip-flop pairs between TCK and reset

Receiver signal probing using a shared probe point

Reduced signaling interface method and apparatus

Reduced signaling interface method and apparatus

Semiconductor device and test method thereof

Semiconductor integrated circuit

Methods and apparatus that selectively use or bypass a remote pin electronics block to test at least one device under test

Local and global address compare with tap interface TDI/TDO lead

Providing A Duplicate Test Signal Of An Output Signal Under Test In An Integrated Circuit

Disabling unused IO resources in platform-based integrated circuits

Semiconductor device and semiconductor device module

Memory wrap test mode using functional read/write buffers

Method for characterizing integrated circuits for identification or security purposes

Semiconductor device and test method thereof

Sampling mechanism for data acquisition counters

Film-type semiconductor package and method using test pads shared by output channels, and test device, semiconductor device and method using patterns shared by test channels

Library test circuit and library test method

Testing target resistances in circuit assemblies

PARAMETRIC MEASURING CIRCUIT FOR MINIMIZING OSCILLATION EFFECT

Method for testing a circuit unit and test apparatus

Parametric measuring circuit for minimizing oscillation effect

Addressable tap domain selection circuit with TDI/TDO external terminal

Semiconductor device with termination resistor circuit

Disabling unused IO resources in platform-based integrated circuits

Universal binding post

High-speed interface circuit test module, module under high-speed interface circuit test, and high-speed interface circuit test method

Integrated circuit device

Die-to-die and chip-to-chip connectivity monitoring

Input/output voltage testing with boundary scan bypass

Device monitoring using satellite ADCS having local voltage reference

Device monitoring using satellite ADCs having local voltage reference

Device monitoring using satellite ADCs having local capacitors

System and method for array diagnostics in superconducting integrated circuit

Systems and methods for automatic test pattern generation for integrated circuit technologies