171856 ⎘
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere; Testing of electronic circuits, e.g. by signal tracer; Testing of digital circuits; Functional testing; Generation of test inputs, e.g. test vectors, patterns or sequences computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging
HARDWARE DECODER FOR RUN-LENGTH ENCODED MASK BITS FOR IN-SYSTEM AUTOMATIC TEST PATTERN GENERATION (ATPG)
#2METHOD OF USING A TEST PATTERN FOR TESTING FUNCTIONALITIES OF EXTERNAL DEVICES WHEN AN ITEM IS ATTACHED TO A VEHICLE
#3GENERATING STRUCTURED TEST VECTOR SEQUENCES FOR LOGIC VERIFICATION
#4EXPERIMENT-IN-THE-LOOP SYSTEM FOR FAST AND EFFECTIVE TUNING OF ACTIVE VIBRATION CONTROLLERS
#5INTEGRATED HARDWARE-IN-THE-LOOP (HIL) SYSTEM FOR TESTING HARDWARE DEVICES AND A METHOD THEREOF
#6AUTOMATED TEST EQUIPMENT AND METHOD USING A TRIGGER GENERATION
#7INTEGRATED-CIRCUIT CHIP FOR RETENTION CELL TESTING
#8AUTOMATED TEST EQUIPMENT, DEVICE UNDER TEST, TEST SETUP METHODS USING AN ACKNOWLEDGE SIGNALING
#9OPTICAL TUNING TEST SYSTEM USING PARALLEL OVEN PIPELINES WITH PARALLEL INSTRUMENT CHANNELS AND MACHINE LEARNING ASSISTANCE
#10Method and System of Developing and Executing Test Program for Verifying DUT
#11AUTOMATED TEST PATTERN GENERATION FOR TESTING DESIGN REDACTING RECONFIGURABLE HARDWARE
#12Deep learning-based MLCC stacked alignment inspection system and method
#13LOW POWER ENVIRONMENT FOR HIGH PERFORMANCE PROCESSOR WITHOUT LOW POWER MODE
#14IP CORE TESTING APPARATUS
#15Hybrid solver for integrated circuit diagnostics and testing
#16Method, device and system for measuring frequency domain characteristics, and storage medium
#17IN-FIELD LATENT FAULT MEMORY AND LOGIC TESTING USING STRUCTURAL TECHNIQUES
#18TUNING A DEVICE UNDER TEST USING PARALLEL PIPELINE MACHINE LEARNING ASSISTANCE
#19Programmable scan chain debug technique
#20Electronic tester and testing method
#21AUTOMATED TEST EQUIPMENT AND METHOD USING A TRIGGER GENERATION
#22Tests for integrated circuit (IC) chips
#23Parameter space reduction for device testing
#24System and method for formal fault propagation analysis
#25Apparatus and system for debugging solid-state disk (SSD) device
#26GENERAL DIGITAL SIGNAL PROCESSING WAVEFORM MACHINE LEARNING CONTROL APPLICATION
#27Compiler-based code generation for post-silicon validation
#28Method and system for efficient testing of digital integrated circuits
#29Test architecture for electronic circuits, corresponding device and method
#30Test circuit
#31Transition fault testing of functionally asynchronous paths in an integrated circuit
#32Device under test synchronization with automated test equipment check cycle
#33Method for testing a digital electronic circuit to be tested, corresponding test system and computer program product
#34Vision system for an automated test system
#35Flexible test systems and methods
#36Deterministic stellar built-in self test
#37System and method for generating test scripts
#38Vector Eyes
#39DIAGNOSTIC TOOL FOR TRAFFIC CAPTURE WITH KNOWN SIGNATURE DATABASE
#40TEST PATTERN GENERATING METHOD, TEST PATTERN GENERATING DEVICE AND FAULT MODEL GENERATING METHOD
#41Automated test equipment for testing one or more devices under test, method for automated testing of one or more devices under test, and computer program for handling command errors
#42Signal path calibration of a hardware setting in a test and measurement instrument
#43Automated test equipment for testing one or more devices under test, method for automated testing of one or more devices under test, and computer program using a buffer memory
#44Motor emulator
#45Automated test equipment using an on-chip-system test controller
#46Automated test equipment for testing high-power electronic components
#47Voltage driver with supply current stabilization
#48Voltage driver circuit
#49Test circuit for dynamic checking for faults on functional and BIST clock paths to memory in both ATPG and LBIST modes
#50Automatic testbench generator for test-pattern validation
#51Techniques in ensuring functional safety (fusa) systems
#52Disaggregated distributed measurement analysis system using dynamic application builder
#53System and method for formal fault propagation analysis
#54Method for a computer-aided automated verification of requirements
#55Combinatorial serial and parallel test access port selection in a JTAG interface
#56Integrated protocol analyzer configured within automated test equipment (ate) hardware
#57Method for calibrating channel delay skew of automatic test equipment
#58Test interface boards, test systems, and methods of operating test interface boards
#59Smart and efficient protocol logic analyzer configured within automated test equipment (ATE) hardware
#60Narrow-parallel scan-based device testing
#61Transistion fault testing of funtionally asynchronous paths in an integrated circuit
#62Ensuring completeness of interface signal checking in functional verification
#63Ensuring completeness of interface signal checking in functional verification
#64Combinatorial serial and parallel test access port selection in a JTAG interface
#65Circuit structures to resolve random testability
#66Circuit structures to resolve random testability
#67Systems and methods for testing an embedded controller
#68Test circuit to debug missed test clock pulses
#69Blade centric automatic test equipment system
#70Blade centric automatic test equipment system
#71Blade centric automatic test equipment system
#72Methods and systems for generating functional test patterns for manufacture test
#73Automatic test-pattern generation for memory-shadow-logic testing
#74Methods and systems for generating functional test patterns for manufacture test
#75Granular dynamic test systems and methods
#76Transition test generation for detecting cell internal defects
#77Method, device and computer program product for circuit testing
#78Methods and systems for circuit fault diagnosis
#79Automated test equipment for testing a device under test and method for testing a device under test
#80Test point insertion for low test pattern counts
#81Staged buffer caching in a system for testing a device under test
#82Online design validation for electronic devices
#83Automatic test-pattern generation for memory-shadow-logic testing
#84Test pattern generation device, fault detection system, test pattern generation method, program and recording medium
#85Test generation for test-per-clock
#86Method and apparatus for device testing using multiple processing paths
#87CLOUD BASED INFRASTRUCTURE FOR SUPPORTING PROTOCOL RECONFIGURATIONS IN PROTOCOL INDEPENDENT DEVICE TESTING SYSTEMS
#88Tester with mixed protocol engine in a FPGA block
#89Systems and methods for dynamic scan scheduling
#90Reducing power consumption during manufacturing test of an integrated circuit
#91Method And Apparatus For Designing A Custom Test System
#92AUTOMATICALLY GENERATING EXECUTABLE CODE FOR A TEST SEQUENCE
#93Automatic test-pattern generation for memory-shadow-logic testing
#94Root cause distribution determination based on layout aware scan diagnosis results
#95Method and device for selectively adding timing margin in an integrated circuit
#96Method and device for selectively adding timing margin in an integrated circuit
#97Method and device for selectively adding timing margin in an integrated circuit
#98Integrated circuit, simulation apparatus and simulation method
#99Test pattern generating method, device, and program
#100Don't-care-bit identification method and don't-care-bit identification program
#101DIAGNOSTIC APPARATUS, DIAGNOSTIC METHOD AND TEST APPARATUS
#102Method and structure to develop a test program for semiconductor integrated circuits
#103Method and apparatus for generating self-verifying device scenario code
#104Test apparatus, test method, program, and recording medium reducing the influence of variations
#105Test pattern generation method for avoiding false testing in two-pattern testing for semiconductor integrated circuit
#106Diagnostic device, diagnostic method, program, and recording medium
#107GENERATING WORST CASE BIT PATTERNS FOR SIMULTANEOUS SWITCHING NOISE (SSN) IN DIGITAL SYSTEMS
#108Method and system for testing an electronic circuit to identify multiple defects
#109Method and system for LBIST testing of an electronic circuit
#110Method and product for testing a device under test
#111Method And Apparatus For Designing A Custom Test System
#112Methods and apparatus for patternizing device responses
#113Method and device for selectively adding timing margin in an integrated circuit
#114Test instrument network
#115SYSTEMS AND METHODS FOR VALIDATING POWER INTEGRITY OF INTEGRATED CIRCUITS
#116Test apparatus, pattern generator, test method and pattern generating method
#117Complex pattern generator for analysis of high speed serial streams
#118System and method for automation of hardware signal characterization and signal integrity verification
#119METHOD FOR AUTOMATIC TEST PATTERN GENERATION FOR ONE TEST CONSTRAINT AT A TIME
#120Integrated testing apparatus, systems, and methods
#121Segmented algorithmic pattern generator
#122TEST EMULATOR, TEST MODULE EMULATOR AND RECORD MEDIUM STORING PROGRAM THEREIN
#123TEST EMULATOR, TEST MODULE EMULATOR AND RECORD MEDIUM STORING PROGRAM THEREIN
#124Generating scan test vectors for proprietary cores using pseudo pins
#125Method of improving electronic component testability rate
#126Method and apparatus for interactive generation of device response templates and analysis
#127Electronic device testing system
#128Method and apparatus for automatically formatting data based on a best match test result type
#129Method of test pattern generation in IC design simulation system
#130Test device with test parameter adaptation
#131Test pattern generating apparatus, circuit designing apparatus, test pattern generating method, circuit designing method, test pattern generating program and circuit designing program
#132Test program set generation tool
#133Method and system for performing installation and configuration management of tester instrument modules
#134Scoring mechanism for automatically generated test programs
#135Systems and methods of test case generation with feedback
#136Test-pattern generation system, test-pattern analysis system, test-pattern generation method, test-pattern analysis method, and computer product
#137Maximum change data pattern
#138Decision selection and associated learning for computing all solutions in automatic test pattern generation (ATPG) and satisfiability
#139Segmented algorithmic pattern generator
#140Algorithm pattern generator for testing a memory device and memory tester using the same
#141Device testing using multiple test kernels
#142Random code generation using genetic algorithms
#143Method and structure to develop a test program for semiconductor integrated circuits
#144Method and structure to develop a test program for semiconductor integrated circuits
#145Semiconductor integrated circuit verification method and test pattern preparation method
#146Method for automatically searching for functional defects in a description of a circuit
#147Methods and apparatus for transforming sequential logic designs into equivalent combinational logic
#148Pseudo random test pattern generation using Markov chains
#149Method and system for automatically creating tests
#150Method and apparatus for case-based learning
#151Test emulator, test module emulator, and record medium storing program therein
#152Method and apparatus for solving bit-slice operators
#153Method and system for controlling interchangeable components in a modular test system
#154Multiple clock and clock cycle selection for x-tolerant logic built in self test (XLBIST)
#155Deterministic data latency in serializer/deserializer-based design for test systems
#156Integrated circuit design modification for localization of scan chain defects
#157Systems and methods to generate a test bench for electrostatic discharge analysis of an integrated circuit design
#158Method and system for generating validation tests
#159Highly accurate defect identification and prioritization of fault locations
#1602D compression-based low power ATPG
#161Area-efficient performance monitors for adaptive voltage scaling
#162Apparatus and method for operating automated test equipment (ATE)