171855 ⎘
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere; Testing of electronic circuits, e.g. by signal tracer; Testing of digital circuits; Functional testing Generation of test inputs, e.g. test vectors, patterns or sequences
Sub-classes:METHOD AND APPARATUS FOR FAULT DETECTING OF INVERTER
#2SEMICONDUCTOR DEVICE, TEST APPARATUS AND METHOD FOR TESTING SEMICONDUCTOR CHIP
#3ELECTRONIC DEVICE AND METHOD THAT APPLIES STRESS TO TRANSISTORS
#43D TAP & SCAN PORT ARCHITECTURES
#5IN-SYSTEM TESTING FOR AUTONOMOUS SYSTEMS AND APPLICATIONS
#6GENERATING A TEST PROGRAM
#7TECHNOLOGIES FOR AUTOMATED TEST PATTERN GENERATION FOR LOGIC CIRCUITS WITH BOOLEAN SATISFIABILITY ANALYSIS
#8TEST MODE CONTROL CIRCUIT, SEMICONDUCTOR APPARATUS AND SYSTEM, AND METHOD THEREOF
#9METHOD, DEVICE, AND SYSTEM FOR DETECTING FUSE CONFIGURATION FOR TRIMMING CIRCUIT
#10GRPC-Based Chip Test Method, GRPC-Based Chip Test Apparatus, and Storage Medium
#113D tap and scan port architectures
#12Method for generating a signal test specification, data processing circuit, and cloud system
#13Bias generator testing using grouped bias currents
#143D TAP and scan port architectures
#15System for testing antenna-in-package modules and method for using the same
#16Parameter space reduction for device testing
#17System testing using partitioned and controlled noise
#18Test method and apparatus of communication chip, device and medium
#19Baseboard management controller (BMC) test system and method
#20Methods and systems for high bandwidth communications interface
#21Linearity test system, linearity signal providing device, and linearity test method
#22Test circuit
#23Single pin DFT architecture for USBPD ICs
#24Semiconductor integrated circuit device and operating method thereof
#25Error detection device and error detection method
#26EVALUATION METHOD FOR HOT CARRIER EFFECT DEGRADED PERFORMANCE
#27Diagnostic enhancement for multiple instances of identical structures
#28INPUT-OUTPUT DEVICE WITH DEBUG CONTROLLER
#293D tap and scan port architectures
#30Digital Input and Output Signal Test Platform
#31Re-programmable self-test
#32Failure diagnostic apparatus and failure diagnostic method
#33Method, apparatus and storage medium for testing chip, and chip thereof
#34Trajectory-optimized test pattern generation for built-in self-test
#35Method of and an arrangement for analyzing manufacturing defects of multi-chip modules made without known good die
#36Method, system and computer program product for introducing personalization data in nonvolatile memories of a plurality of integrated circuits
#373D tap and scan port architectures
#38Dynamically power noise adaptive automatic test pattern generation
#39Systems on chips, integrated circuits, and operating methods of the integrated circuits
#40Pathloss mitigation via simulated models of dynamic environments
#413D tap and scan port architectures
#42Fault detection of a system using a test input comprising a linear combination of inputs of the system
#43Systems and methods for performing a fast simulation
#44Current measurement apparatus including charge/discharge means and current measurement method using same
#45Generation of patterns for identifying faults in power supply systems
#46Testing an array of integrated circuits formed on a substrate sheet
#47TEST DEVICE, TEST METHOD, AND COMPUTER READABLE MEDIUM
#48Memory circuit march testing
#49Re-programmable self-test
#50Method and system to assure monitoring system validity
#51Up control, CSU circuit, scan circuit, up signal contact point
#52Test mode set circuit and method of semiconductor device
#53Re-programmable self-test
#543D tap and scan port architectures
#55Methods and systems for high bandwidth communications interface
#56Single circuit fault detection
#573D tap and scan port architectures
#58In-field self-test controller for safety critical automotive use cases
#59Method of testing semiconductor devices and system for testing semiconductor devices
#60Device and method for robustness verification
#61Built-in device testing of integrated circuits
#62Multiple-level driver circuit with non-commutating bridge
#63Detection points of a printed circuit board to determine electrical parameter of an integrated circuit
#64Implementing decreased scan data interdependence in on product multiple input signature register (OPMISR) through PRPG control rotation
#65BTI degradation test circuit
#66Die top, bottom parallel/serial date with test and scan circuitry
#67Test point circuit, scan flip-flop for sequential test, semiconductor device and design device
#68Interleaver ic with up control and capture, shift, update circuitry
#69Method and apparatus for test time reduction using fractional data packing
#70Method and apparatus for evaluating and optimizing a signaling system
#71Detecting device and detecting method for detecting output impedance angle of inverter
#72Tap, test, CSU, scan circuitry with top and bottom contacts
#73Methods and systems for circuit fault diagnosis
#74IC die with tap lock, test, scan, and up circuitry
#75Method and system for performing electrical tests on complex devices
#76IC die test, scan, and capture, shift, and update circuitry
#77Semiconductor apparatus
#78IC die top, bottom signals, tap lock, test, scan circuitry
#79Method and apparatus for test time reduction using fractional data packing
#80Multi-bank digital stimulus response in a single field programmable gate array
#81System and method for statistical post-silicon validation
#82Parametric test program generator
#83PROGRAMMABLE LOGIC DEVICE AND VERIFICATION METHOD THEREFOR
#84Arithmetic logic unit testing system and method
#85Method and apparatus for evaluating and optimizing a signaling system
#86Methods and systems to measure a signal on an integrated circuit die
#87Sequential logic sensitization from structural description
#88Systems and methods for dynamic scan scheduling
#89SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
#90IC scan and test circuitry with up control circuitry
#91Embedded processor
#92Termination circuit, semiconductor device, and test system
#93Integrated circuits capable of generating test mode control signals for scan tests
#94Method and apparatus for evaluating and optimizing a signaling system
#95Methods and systems for logic device defect tolerant redundancy
#96Modeling test space for system behavior with optional variable combinations
#97Root cause distribution determination based on layout aware scan diagnosis results
#98Embedded processor
#99Methods and systems to measure a signal on an integrated circuit die
#100Method and apparatus for evaluating and optimizing a signaling system
#101Method for testing a partially assembled multi-die device, integrated circuit die and multi-die device
#102Semiconductor integrated circuit device
#103Embedded processor
#104Enforcing Worst-Case Behavior During Transmit Channel Analysis
#105Method and apparatus for evaluating and optimizing a signaling system
#106Don't-care-bit identification method and don't-care-bit identification program
#107Method and structure to develop a test program for semiconductor integrated circuits
#108METHOD AND SYSTEM FOR EMULATING A DESIGN UNDER TEST ASSOCIATED WITH A TEST ENVIRONMENT
#109System, computer program product and method for testing a logic circuit
#110Implementing diagnosis of transitional scan chain defects using logic built in self test LBIST test patterns
#111Embedded processor
#112System and method for power reduction through power aware latch weighting
#113Semiconductor integrated circuit device
#114Test vector generating method and test vector generating program of semiconductor logic circuit device
#115Method and product for testing a device under test
#116TEST PATTERN CUSTOMIZATION OF HIGH SPEED SAS NETWORKS IN A MANUFACTURING TEST SYSTEM
#117Generating worst case test sequences for non-linearly driven channels
#118EVENT TIMING ANALYZER FOR A SYSTEM OF INSTRUMENTS AND METHOD OF ANALYZING EVENT TIMING IN A SYSTEM OF INTRUMENTS
#119Bit pattern synchronization in acquired waveforms
#120System and method for encoder failure detection
#121Apparatus and method for generating test signals after a test mode is completed
#122System and method for performing processing in a testing system
#123System and method for performing processing in a testing system
#124System and method for performing processing in a testing system
#125System and method for performing processing in a testing system
#126Apparatus and Method For Generating Test Pattern Data For Testing Semiconductor Device
#127Apparatus to facilitate functional shock and vibration testing of device connections and related method
#128System and method for performing processing in a testing system
#129System and method for performing processing in a testing system
#130TEST EMULATOR, TEST MODULE EMULATOR AND RECORD MEDIUM STORING PROGRAM THEREIN
#131TEST EMULATOR, TEST MODULE EMULATOR AND RECORD MEDIUM STORING PROGRAM THEREIN
#132Iterative process for identifying systematics in data
#133Method and machine-readable media for inferring relationships between test results
#134Method and system for managing access to a data store
#135Methods and systems for derivation of missing data objects from test data
#136METHOD AND APPARATUS FOR EVALUATING AND OPTIMIZING A SIGNALING SYSTEM
#137Method and apparatus for evaluating and optimizing a signaling system
#138SYSTEM AND METHOD FOR TESTING A NAS
#139Test device with test parameter adaptation
#140Multiple function results using single pattern and method
#141Method and apparatus for evaluating and optimizing a signaling system
#142ROM emulator
#143Verification circuitry for master-slave system
#144Signal generator provided with license control function and license control method thereof
#145Establishing a reference bit in a bit pattern
#146Circuit test pattern edition apparatus, circuit test pattern editing method, and signal-bearing medium embodying a program of circuit test pattern edition
#147Multi-domain execution of tests on electronic devices
#148Method and system for performing installation and configuration management of tester instrument modules
#149Test apparatus
#150Generation of test vectors for testing electronic circuits taking into account of defect probability
#151Apparatus to facilitate functional shock and vibration testing of device connections and related method
#152Test simulator, test simulation program and recording medium
#153System for testing digital components
#154Generating test patterns used in testing semiconductor integrated circuit
#155Maximum change data pattern
#156Generating test patterns used in testing semiconductor integrated circuit
#157Generating test patterns used in testing semiconductor integrated circuit
#158Method and apparatus for generating test signals
#159System and method for generating a jittered test signal
#160Single-pass methods for generating test patterns for sequential circuits
#161Method and structure to develop a test program for semiconductor integrated circuits
#162Method and structure to develop a test program for semiconductor integrated circuits
#163Pseudo random verification of waveform fault coverage
#164Test emulator, test module emulator, and record medium storing program therein
#165Method and system for controlling interchangeable components in a modular test system
#166Deterministic data latency in serializer/deserializer-based design for test systems
#167Securing access to integrated circuit scan mode and data
#168System, method, and computer program for combining results of event processing received from a plurality of virtual servers
#169Generating test scenarios from application-layer messages