171861 ⎘
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere; Testing of electronic circuits, e.g. by signal tracer; Testing of digital circuits; Functional testing; Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
Sub-classes:BACKSIDE POWER RAIL FOR PHYSICAL FAILURE ANALYSIS (PFA)
#2METHOD AND DEVICE OF MANUFACTURING SEMICONDUCTOR DEVICE
#3SYSTEM AND METHOD FOR FAULT SEQUENCE RECORDING
#4System and method for fault sequence recording
#5Automatic test pattern generation-based circuit verification method and apparatus
#6Deep learning-based MLCC stacked alignment inspection system and method
#7SYSTEMS AND METHODS TO DETECT CELL-INTERNAL DEFECTS
#8Stress-testing electrical components using telemetry modeling
#9Signal toggling detection and correction circuit
#10Backside power rail for physical failure analysis (PFA)
#11Noise-compensated jitter measurement instrument and methods
#12Systems and methods to detect cell-internal defects
#13Systems and methods to detect cell-internal defects
#14Vector Eyes
#15Systems and methods for false-positive reduction in power electronic device evaluation
#16Trajectory-optimized test pattern generation for built-in self-test
#17Power electronic circuit fault diagnosis method based on extremely randomized trees and stacked sparse auto-encoder algorithm
#18Apparatus and methods for testing circuit elements at one or more manufacturing stages
#19Measurement system as well as method of providing statistical information
#20Measurement gap communication
#21Predictive analytics of device performance
#22ALTERNATIVE TECHNIQUES FOR DESIGN OF EXPERIMENTS
#23Multi-stage machine learning-based chain diagnosis
#24Input data compression for machine learning-based chain diagnosis
#25Predictive analytics of device performance
#26Functional diagnostics based on dynamic selection of alternate clocking
#27Circuit structures to resolve random testability
#28Circuit structures to resolve random testability
#29Flip flop of a digital electronic chip
#30Systems and methods for testing an embedded controller
#31Mapping physical shift failures to scan cells for detecting physical faults in integrated circuits
#32Cell-aware diagnostic pattern generation for logic diagnosis
#33Increasing compression by reducing padding patterns
#34Method and system for functional safety verification
#35Dynamic fault model generation for diagnostics simulation and pattern generation
#36Semiconductor power and performance optimization
#37Automatic test-pattern generation for memory-shadow-logic testing
#38Testing storage device power circuitry
#39Method and apparatus for generating featured test pattern
#40Method and apparatus for validating a test pattern
#41Methods and systems for circuit fault diagnosis
#42Circuit division method for test pattern generation and circuit division device for test pattern generation
#43Testing storage device power circuitry
#44Test point insertion for low test pattern counts
#45System for and method of semiconductor fault detection
#46Staged buffer caching in a system for testing a device under test
#47Isometric test compression with low toggling activity
#48Method and apparatus for generating featured scan pattern
#49Automatic test-pattern generation for memory-shadow-logic testing
#50Linear decompressor with two-step dynamic encoding
#51Comparison device and method for comparing test pattern files of a wafer tester
#52Signal selection apparatus and system, and circuit emulator and method and program
#53Integrated circuit leakage power reduction using enhanced gated-Q scan techniques
#54Methods and systems for simulating circuit operation
#55Method and system for test vector generation
#56Automatic test-pattern generation for memory-shadow-logic testing
#57Root cause distribution determination based on layout aware scan diagnosis results
#58Method and apparatus for generating test patterns for use in at-speed testing
#59Method and system for identifying power defects using test pattern switching activity
#60Integrated circuit leakage power reduction using enhanced gated-Q scan techniques
#61Profiling-based scan chain diagnosis
#62Method and apparatus for determining a calibration signal
#63Method and apparatus for generating test patterns for use in at-speed testing
#64Cell-Aware Fault Model Creation And Pattern Generation
#65Method and structure to develop a test program for semiconductor integrated circuits
#66Test apparatus, test method, program, and recording medium reducing the influence of variations
#67Diagnostic device, diagnostic method, program, and recording medium
#68System and Method for Automatically Testing a Model
#69Signal selection apparatus and system, and circuit emulator and method and program
#70Method for determining features associated with fails of integrated circuits
#71System and Method For Testing a Control Unit System
#72Method and apparatus for testing integrated circuits by employing test vector patterns that satisfy passband requirements imposed by communication channels
#73Test Apparatus for Control Unit, Pattern Signal Creating Apparatus, and Test Program Generating Apparatus
#74Fault location estimation system, fault location estimation method, and fault location estimation program for multiple faults in logic circuit
#75Circuit and Method for Physical Defect Detection of an Integrated Circuit
#76ITERATIVE TEST GENERATION AND DIAGNOSTIC METHOD BASED ON MODELED AND UNMODELED FAULTS
#77METHOD AND SYSTEM FOR TEST VERIFICATION OF INTEGRATED CIRCUIT DESIGNS
#78Systems and methods for improved scan testing fault coverage
#79TEST EMULATOR, TEST MODULE EMULATOR AND RECORD MEDIUM STORING PROGRAM THEREIN
#80TEST EMULATOR, TEST MODULE EMULATOR AND RECORD MEDIUM STORING PROGRAM THEREIN
#81Fault list and test pattern generating apparatus and method, fault list generating and fault coverage calculating apparatus and method
#82Method and apparatus for supporting verification, and computer product
#83Speeding up defect diagnosis techniques
#84Technique for generating input stimulus to cover properties not covered in random simulation
#85Apparatus for storing variable values to provide context for test results that are to be formatted
#86Method and device for supporting verification, and computer product
#87Integrated circuit test simulator
#88Method for identifying a physical failure location on an integrated circuit
#89Method and system for debug and test using replicated logic
#90Digital system and method for testing analogue and mixed-signal circuits or systems
#91Interface configurable for use with target/initiator signals
#92Method and apparatus for supporting verification, and computer product
#93Processor condition sensing circuits, systems and methods
#94Defect diagnosis for semiconductor integrated circuits
#95Built-in self-test emulator
#96Built-in self-test emulator
#97Method and system for simulating a modular test system
#98Smart capture for ATPG (automatic test pattern generation) and fault simulation of scan-based integrated circuits
#99Method for localization and generation of short critical sequence
#100Path delay test method
#101Method and system for delay defect location when testing digital semiconductor devices
#102Method and apparatus for encoding and generating transaction-based stimulus for simulation of VLSI circuits
#103Automated BIST test pattern sequence generator software system and method
#104Method and structure to develop a test program for semiconductor integrated circuits
#105Method and structure to develop a test program for semiconductor integrated circuits
#106Directed falsification of a circuit
#107Circuit verification using multiple engines
#108Methods and apparatus for transforming sequential logic designs into equivalent combinational logic
#109Cost estimation for device testing
#110Adaptable circuit blocks for use in multi-block chip design
#111Test emulator, test module emulator, and record medium storing program therein
#112Method and system for controlling interchangeable components in a modular test system
#113Methods and systems for automatic verification of specification document to hardware design
#114Adaptive cell-aware test model for circuit diagnosis
#115Utilizing single cycle ATPG test patterns to detect multicycle cell-aware defects
#116Unified approach for improved testing of low power designs with clock gating cells
#117Vulnerability determination in circuits
#118Automated waveform analysis methods using a parallel automated development system
#119Automated waveform analysis methods using a parallel automated development system
#120Automated waveform analysis using a parallel automated development system
#121Automated waveform analysis using a parallel automated development system
#122System and methods for simulating a circuit design
#123Implementing synchronous triggers for waveform capture in an FPGA prototyping system