171864 ⎘
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere; Testing of electronic circuits, e.g. by signal tracer; Testing of digital circuits; Functional testing; Generation of test inputs, e.g. test vectors, patterns or sequences as a result of hardware simulation, e.g. in an HDL environment
POWER-HARDWARE-IN-THE-LOOP SIMULATION SYSTEM AND METHOD AND NON-TRANSITORY COMPUTER READABLE MEDIUM
#2CO-DEBUG OF PROCESSING CONDITIONS OF LOGIC DEVICES
#3Data traffic injection for simulation of circuit designs
#4Reduced signaling interface method and apparatus
#5Integrated circuit with reduced signaling interface
#6Reduced signaling interface circuit
#7Automatic testbench generator for test-pattern validation
#8Low cost design for test architecture
#9Entering home state after soft reset signal after address match
#10System architecture method and apparatus for adaptive hardware fault detection with hardware metrics subsystem
#11Apparatus and method for performing a scalability check on a hardware description language representation of a circuit
#12Mapping physical shift failures to scan cells for detecting physical faults in integrated circuits
#13Address/instruction registers, target domain interfaces, control information controlling all domains
#14Transition test generation for detecting cell internal defects
#15Low cost design for test architecture
#16Addressable tap domain selection circuit with instruction and linking circuits
#17Using computer-aided design layout in scanning system
#18Method and apparatus for validating a test pattern
#19Method and system for performing electrical tests on complex devices
#20TAP addressable circuit with bi-directional TMS and second signal lead
#21System for and method of semiconductor fault detection
#22Generation of test stimuli
#23Linking circuitry selectively coupling TDI/TDO with first and second domains
#24Modeling test space for system behavior with optional variable combinations
#25Method and system for implementing parallel execution in a computing system and in a circuit simulator
#26Method and system for implementing parallel execution in a computing system and in a circuit simulator
#27Computer-aided design system to automate scan synthesis at register-transfer level
#28Method of analyzing the safety of a device employing on target hardware description language based fault injection
#29Address and instruction controller with TCK, TMS, address match inputs
#30Method and device for selectively adding timing margin in an integrated circuit
#31Method and device for selectively adding timing margin in an integrated circuit
#32Method and device for selectively adding timing margin in an integrated circuit
#33METHOD AND SYSTEM FOR IMPLEMENTING, CONTROLLING, AND INTERFACING WITH CIRCUIT SIMULATORS
#34Method and system for implementing circuit simulators
#35Inverter and TMS clocked flip-flop pairs between TCK and reset
#36Design verification apparatus and design verification program
#37Computer-aided design system to automate scan synthesis at register-transfer level
#38Reduced signaling interface method and apparatus
#39METHOD FOR INTEGRATED CIRCUIT DESIGN VERIFICATION IN A VERIFICATION ENVIRONMENT
#40Multiprocessor computer system and method having at least one processor with a dynamically reconfigurable instruction set
#41TEST METHOD, TEST CONTROL PROGRAM AND SEMICONDUCTOR DEVICE
#42Bridge fault removal apparatus, bridge fault removal method, and computer readable medium comprising computer program code for removing bridge fault
#43Method and system for debugging using replicated logic and trigger logic
#44Reduced signaling interface method and apparatus
#45Method and apparatus for evaluating integrated circuit design performance using basic block vectors, cycles per instruction (CPI) information and microarchitecture dependent information
#46Autonomic verification of HDL models using real-time statistical analysis and layered feedback stages
#47Links and chains verification and validation methodology for digital devices
#48Local and global address compare with tap interface TDI/TDO lead
#49Method and system for testing functionality of a chip checker
#50Generating a worst case current waveform for testing of integrated circuit devices
#51Apparatus and Method for Verifying Pattern of Semiconductor Device
#52Method and device for selectively adding timing margin in an integrated circuit
#53ACCELERATED LIFE TESTING OF SEMICONDUCTOR CHIPS
#54Integrated circuit test method and test apparatus
#55Generating coverage data for a switch frequency of HDL or VHDL signals
#56Apparatus for testing semiconductor integrated circuit and method for testing semiconductor integrated circuit
#57Importation of virtual signals into electronic test equipment to facilitate testing of an electronic component
#58Monitoring software simulations of hardware systems
#59Dynamic domain abstraction through meta-analysis
#60Troubleshooting temporal behavior in “combinational” circuits
#61System for and method of integrating test structures into an integrated circuit
#62METHOD TO IDENTIFY AND GENERATE CRITICAL TIMING PATH TEST VECTORS
#63Method for generating compiler, simulation, synthesis and test suite from a common processor specification
#64Automated Circuit Model Generator
#65Property description coverage measuring apparatus
#66Random test generation using an optimization solver
#67Computer-aided design system to automate scan synthesis at register-transfer level
#68Requirements-based test generation
#69ITERATIVE TEST GENERATION AND DIAGNOSTIC METHOD BASED ON MODELED AND UNMODELED FAULTS
#70Circuit designing program and circuit designing system having function of test point insertion
#71Method for verifying interconnected blocks of IP
#72Testing of embedded systems
#73Method for local hot spot fixing
#74Testing Suite for Product Functionality Assurance and Guided Troubleshooting
#75Method and system for debugging using replicated logic and trigger logic
#76Method for testing a hardware circuit block written in a hardware description language
#77Apparatus and method for unified debug for simulation
#78Importation of virtual signals into electronic test equipment to facilitate testing of an electronic component
#79Semiconductor integrated circuit and method of fabricating the same
#80System and method of automating the addition of programmable breakpoint hardware to design models
#81System and method for complex programmable breakpoints using a switching network
#82Semiconductor device, and design method, inspection method, and design program therefor
#83Method and system for debug and test using replicated logic
#84Logic circuit design method, computer-readable recording medium having logic circuit design program stored therein, and logic circuit design device
#85Method and system for debugging an electronic system
#86Method and system for debugging using replicated logic and trigger logic
#87Addressable tap domain selection circuit with TDI/TDO external terminal
#88Microprocessor architected state signature analysis
#89Method and apparatus of fault diagnosis for integrated logic circuits
#90Database mining method and computer readable medium carrying instructions for coverage analysis of functional verification of integrated circuit designs
#91SRAM ring oscillator
#92Hardware/software design tool and language specification mechanism enabling efficient technology retargeting and optimization
#93Smart capture for ATPG (automatic test pattern generation) and fault simulation of scan-based integrated circuits
#94Virtual test environment
#95Computer-aided design system to automate scan synthesis at register-transfer level
#96Model specific register operations
#97Circuit analyzing device, circuit analyzing method, program, and computer readable information recording medium considering influence of signal input to peripheral circuit which does not have logical influence
#98Method and system for selective compilation of instrumentation entities into a simulation model of a digital design
#99Hardware debugging in a hardware description language
#100Database mining system and method for coverage analysis of functional verification of integrated circuit designs
#101Controller based hardware device and method for setting the same
#102System and method for testing a circuit design
#103Test arrangement for testing semiconductor circuit chips
#104Semiconductor device, and design method, inspection method, and design program therefor
#105Methods and systems for automatic verification of specification document to hardware design
#106Hierarchical access simulation for signaling with more than two state values
#107System and method for accelerating timing-accurate gate-level logic simulation
#108System and methods for simulating a circuit design
#109Implementing synchronous triggers for waveform capture in an FPGA prototyping system
#110Method and apparatus for performing compilation using multiple design flows