171878 ⎘
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere; Testing of electronic circuits, e.g. by signal tracer; Testing of digital circuits; Functional testing; Reconfiguring for testing, e.g. LSSD, partitioning; Test of Sequential circuits Test of flip-flops or latches
ELECTRONIC CIRCUIT AND METHOD OF ERROR CORRECTION
#2SEMICONDUCTOR DEVICE AND METHOD OF TESTING SEMICONDUCTOR DEVICE
#3SYSTEMS AND METHODS FOR SCAN CHAIN INTERFACE FOR NON-VOLATILE STORAGE BITS
#4ELECTRONIC DEVICE AND OPERATION METHOD THEREFOR
#5SYSTEM STATE SAVE AND RESTORE MECHANISM USING HOLD LATCH CELL
#6FLIP-FLOPS FOR CIRCUIT TESTING BASED ON SCAN CHAINS
#7STATE CLEARING OF INTERNAL MEMORY AND FLIP-FLOPS OF A SYSTEM USING BUILT-IN TEST AND SCAN CIRCUITRY
#8BI-DIRECTIONAL SCAN FLIP-FLOP CIRCUIT AND METHOD
#9SEMICONDUCTOR DEVICE AND METHOD OF FAILURE ANALYSIS FOR SEMICONDUCTOR DEVICE
#10TEST DEVICE PERFORMING TEST OPERATION ON LATCH CIRCUIT, OPERATING METHOD OF TEST DEVICE, AND STORAGE DEVICE
#11ARCHITECTURE FOR TESTING MULTIPLE SCAN CHAINS
#12BI-DIRECTIONAL SCAN FLIP-FLOP CIRCUIT AND METHOD
#13Error protection analysis of an integrated circuit
#14ELECTRONIC CIRCUIT AND METHOD OF ERROR CORRECTION
#15MULTIPLEXER FOR SDFQ HAVING DIFFERENTLY-SIZED SCAN AND DATA TRANSISTORS, SEMICONDUCTOR DEVICE INCLUDING SAME AND METHODS OF MANUFACTURING SAME
#16Scan Flip-Flops With Pre-Setting Combinational Logic
#17Integrated circuit with timing correction circuitry
#18DATA INTEGRITY CHECKING
#19AUTOMATED TEST PATTERN GENERATION FOR TESTING DESIGN REDACTING RECONFIGURABLE HARDWARE
#20SYSTEMS AND METHODS FOR SCAN CHAIN INTERFACE FOR NON-VOLATILE STORAGE BITS
#21SEMICONDUCTOR CHIP AND SEQUENCE CHECKING CIRCUIT
#22Bi-directional scan flip-flop circuit and method
#23Scan flip-flops with pre-setting combinational logic
#24Flip-flops and scan chain circuits including the same
#25COMPUTER-READABLE RECORDING MEDIUM STORING TEST PATTERN GENERATION PROGRAM, TEST PATTERN GENERATION APPARATUS, AND TEST PATTERN GENERATION METHOD
#26Registers
#27On-die clock period jitter and duty cycle analyzer
#28Multiplexer for SDFQ having differently-sized scan and data transistors, semiconductor device including same and methods of manufacturing same
#29Electronic circuit and method of error correction
#30Redundancy circuit
#31Integrated circuit with reference sub-system for testing and replacement
#32SEMICONDUCTOR DEVICE AND METHOD OF FAILURE ANALYSIS FOR SEMICONDUCTOR DEVICE
#33Integrated test circuit, test assembly and method for testing an integrated circuit
#34Computer-readable recording medium storing analysis program, analysis method, and analysis device
#35Pseudo-random binary sequences (PRBS) generator for performing on-chip testing and a method thereof
#36Device and method for monitoring data and timing signals in integrated circuits
#37High speed debug-delay compensation in external tool
#38Safety mechanism for digital reset state
#39Double edge triggered Mux-D scan flip-flop
#40Integrated circuit control latch protection
#41SEMICONDUCTOR DEVICE, METHOD FOR DIAGNOSING SEMICONDUCTOR DEVICE, AND DIAGNOSIS PROGRAM FOR SEMICONDUCTOR DEVICE
#42OBFUSCATED SHIFT REGISTERS FOR INTEGRATED CIRCUITS
#43ON-CHIP SEQUENCE PROFILER
#44On-chip sequence profiler
#45Method and system for functional safety verification
#46Apparatus, method, and system for testing IC chip
#47Semiconductor power and performance optimization
#48Semiconductor device, electronic control system and method for evaluating electronic control system
#49Generating test sets for diagnosing scan chain failures
#50Dynamic hard error detection
#51Dynamic hard error detection
#52Fault dictionary based scan chain failure diagnosis
#53Generating test sets for diagnosing scan chain failures
#54Methods for analyzing and adjusting semiconductor device, and semiconductor system
#55FAULTY SITE IDENTIFICATION APPARATUS, FAULTY SITE IDENTIFICATION METHOD, AND INTEGRATED CIRCUIT
#56Device and method for testing integrated circuits
#573-Dimensional method for determining the clock-to-Q delay of a flipflop
#58Locating hold time violations in scan chains by generating patterns on ATE
#59Method and apparatus for testing a ring of non-scan latches with logic built-in self-test
#60Fault dictionary-based scan chain failure diagnosis
#61Generating test sets for diagnosing scan chain failures
#62Apparatus for locating a defect in a scan chain while testing digital logic
#63Process for identifying the location of a break in a scan chain in real time
#64Integrated circuit
#65Minimizing timing skew among chip level outputs for registered output signals
#66Method and apparatus for testing a ring of non-scan latches with logic built-in self-test
#67System and shadow bistable circuits coupled to output joining circuit
#68Self-correcting circuitry
#69Multiplexer for SDFQ having differently-sized scan and data transistors, semiconductor device including same and methods of manufacturing same
#70Core and interface scan testing architecture and methodology
#71Clock control system for scan chains
#72Built-in self test controller for a random number generator core
#73Apparatus and method for testing a scan chain including modifying a first clock signal to simulate high-frequency operation associated with a second clock signal