Semiconductor integrated circuit, test data generating device, LSI test device, and computer product

TAP, ST, lockout, and IR SO enable output data control

Scan frame based test access mechanisms

Scan compression architecture for a design for testability compiler used in system-on-chip software design tools

Fault detection method and apparatus

Systems and methods for improved fault coverage of LBIST testing

Method and apparatus for testing a data processing system

Trading propensity-based clustering of circuit elements in a circuit design

Integrated circuit comprising a test mode secured by the use of an identifier, and associated method

Parallel scan distributors and collectors and process of testing integrated circuits

Semiconductor integrated circuit device and delay fault testing method

DATA STORING

Electronic circuit comprising a test mode secured by the breaking of a test chain, and associated electronic circuit

Scan testing using scan frames with embedded commands

SCANNABLE DOMINO LATCH REDUNDANCY FOR SOFT ERROR RATE PROTECTION WITH COLLISION AVOIDANCE

Efficient scan chain insertion using broadcast scan for reduced bit collisions

Test Method and Test Device for Testing an Integrated Circuit

Electronic circuit and integrated circuit including scan testing circuit, and power consumption reducing method used for integrated circuit

Flexible JTAG architecture

PARALLEL ARCHITECTURE FOR LOW POWER LINEAR FEEDBACK SHIFT REGISTERS

Test circuit and method for hierarchical core

Tap and linking module for scan access of multiple cores with IEEE 1149.1 test access ports

Scan chain extracting method, test apparatus, circuit device, and scan chain extracting program

Semiconductor integrated circuit with test circuit

Low power scan process with connected stimulus and scan paths

Sequential scan technique providing enhanced fault coverage in an integrated circuit

Plural circuit selection using role reversing control inputs

Accelerated scan circuitry and method for reducing scan test data volume and execution time

Method and apparatus for affecting a portion of an integrated circuit

Apparatus with programmable scan chains for multiple chip modules and method for programming the same

Reduced pin count scan chain implementation

Method and system for testing backplanes utilizing a boundary scan protocol

Comparator circuitry connected to input and output of tristate buffer

Systems and methods for LBIST testing using isolatable scan chains

SCAN TESTING SYSTEM, METHOD AND APPARATUS

Method, apparatus and computer program product for implementing scan-chain-specific control signals as part of a scan chain

Electronic circuit comprising a secret sub-module

Systems and methods for diagnosing rate dependent errors using LBIST

Semiconductor integrated circuit design apparatus and semiconductor integrated circuit design method

Method of improving logical built-in self test (LBIST) AC fault isolations

Method and system for protecting processors from unauthorized debug access

Method and apparatus for determining stuck-at fault locations in cell chains using scan chains

Method and apparatus for parameter adjustment, testing, and configuration

Method and apparatus for reducing number of transitions generated by linear feedback shift register

Internal core connected to bond pads by distributor and collector

SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD THEREOF

Method and apparatus for enabling multipoint bus access

Semiconductor integrated circuit incorporating test configuration and test method for the same

Pipelined scan structures for testing embedded cores

BIST with generator, compactor, controller, adaptor, and separate scan paths

Multiple uses for BIST test latches

AC propagation testing preventing sampling test data at Capture-DR state

Apparatus for performing stuck fault testings within an integrated circuit

Systems and methods for LBIST testing using multiple functional subphases

Electronic circuitry protected against transient disturbances and method for simulating disturbances

Debug and test system with format select register circuitry

Multiple device scan chain emulation/debugging

Securing the test mode of an integrated circuit

Sequential signals selecting mode and stopping transfers of interface adaptor

Testing using independently controllable voltage islands

Mask network design for scan-based integrated circuits

Accepting link ID upon supplied and sampled bits matching

Adapter implemented background data transfers while tap in non-scan state

Entering command based on number of states in advanced mode

Zero-bit scans defining command window and control level

Systems and methods for reconfiguring scan chains

Boundary scan circuit with integrated sensor for sensing physical operating parameters

Register file and its storage device

Testing of integrated circuits

Test point insertion method

Methods and computer program products for debugging clock-related scan testing failures of integrated circuits

IC with TAP, STP and lock out controlled output buffer

Processor condition sensing circuits, systems and methods

Integrated circuit

Method and apparatus for selective scan chain diagnostics

Fault diagnosis of compressed test responses having one or more unknown states

Adaptive fault diagnosis of compressed test responses

Fault diagnosis of compressed test responses

First and second scan distributors, collectors, controllers, and multiplexers

System and shadow bistable circuits coupled to output joining circuit

Self-reparable semiconductor and method thereof

Lockstep mechanism to ensure security in hardware at power-up

Connection of auxiliary circuitry to tap and instruction register controls

Scan flip-flop circuit with reduced power consumption

Circuit and method for storing a signal using a latch shared between operational and diagnostic paths

Selecting between two TAP circuits with MODE/TCK and TCK/MODE signals

Dynamically reconfigurable shared scan-in test architecture

Dynamic reconfiguration of a system monitor (DRPORT)

Methods and apparatus for scan insertion

Method and apparatus for designing layout, and computer product

Semiconductor integrated circuit device and test method thereof

Method on scan chain reordering for lowering VLSI power consumption

Methods for debugging scan testing failures of integrated circuits

TAP time division multiplexing with scan test

Self-testing input/output pad

Scan test tools, models and/or methods

Serial data I/O on JTAG TCK with TMS clocking

IC with comparator receiving expected and mask data from pads

Cell with fixed output voltage for integrated circuit

Tap time division multiplexing

Diagnostic method for detection of multiple defects in a Level Sensitive Scan Design (LSSD)

Protecting an integrated circuit test mode

Segmented scan chains with dynamic reconfigurations

Tap sampling at double rate

Tap multiplexer

JTAG circuit transferring data between devices on TMS terminals

Accelerated scan circuitry and method for reducing scan test data volume and execution time

Semiconductor integrated circuit

Semiconductor integrated circuit

Self-timed scan circuit for ASIC fault testing

Scan test circuit

Systems and methods for circuit testing

Microcomputer, a method for protecting memory and a method for performing debugging

Scan test method, device, and system

Adaptable circuit blocks for use in multi-block chip design

Methods and structure for scan testing of secure systems

Mask network design for scan-based integrated circuits

Control of tristate buses during scan test

Scan-mode indication technique for an integrated circuit

Method for separating shift and scan paths on scan-only, single port LSSD latches

JTAG state machines with respective enable input and select input

Semiconductor circuit apparatus and test method thereof

Automatic scan-based testing of complex integrated circuits

Accelerated scan circuitry and method for reducing scan test data volume and execution time

Means scanning scan path parts sequentially and capturing response simultaneously

Wrapper instruction/data register controls from test access or wrapper ports

Configurable delay chain

Scan chain formation for improving chain resolution

Machine-learning-based design-for-test (DFT) recommendation system for improving automatic test pattern generation (ATPG) quality of results (QoR)

Power-sensitive scan-chain testing

DIMM slot test system without series connection of test board through JTAG and method thereof

Systems and methods for scan chain stitching

Localization of multiple scan chain defects per scan chain

Core and interface scan testing architecture and methodology

Scan compression through pin data encoding

Control data registers for scan testing

Method and apparatus for timing-annotated scan-chain testing using parallel testbench

Clock control system for scan chains

Method and apparatus for contemporary test time reduction for JTAG

Machine-learning-based design-for-test (DFT) recommendation system for improving automatic test pattern generation (ATPG) quality of results (QOR)

Programmable test compactor for improving defect determination

Scalable scan architecture for multi-circuit block arrays

Field adaptable in-system test mechanisms

Dynamically protective scan data control

Self-gating flip-flop

Laser-based integrated circuit testing techniques

Securing access to integrated circuit scan mode and data

Physically aware insertion of diagnostic circuit elements

Circuits for and methods of implementing a design for testing and debugging with dual-edge clocking

Scan wrapper circuit for integrated circuit

Methods and apparatuses to enhance timing delay fault coverage with test logic that includes partitions and scan flip-flops

Apparatuses and methods to enhance timing delay fault coverage

Method and system for improving efficiency of XOR-based test compression using an embedded serializer-deserializer

Double data rate in parallel testing

System and method for bit-wise selective masking of scan vectors for -value tolerant built-in self test

Inter-block scan testing with share pads

Clock control circuitry and methods of utilizing the clock control circuitry

Test access architecture for stacked dies

Test access architecture for multi-die circuits