Support device, semiconductor device, and non-transitory computer readable medium

Tap, data input, output circuitry coupled to mode select lead

First and second data communication circuitry operating in different states

Semiconductor device, test structure of the semiconductor device, and method of testing the semiconductor device

Buffer testing for reconfigurable instruction cell arrays

Parallel scan distributors and collectors and process of testing integrated circuits

Blocking the effects of scan chain testing upon a change in scan chain topology

Circuit and method for monolithic stacked integrated circuit testing

Method for scan testing three-dimensional chip

Gating WSP update and TAP updatedr with TAP IR enable

Integrated circuit (IC) for reconstructing values of flip-flops connected in a scan-chain by using a joint test action group (JTAG) interface, a method of operating the IC, and devices having the IC

Processor TAP support for remote services

Interposer monitor coupled to clock, start, enable of monitor trigger

Method and apparatus for providing clock signals for a scan chain

Power supply monitor for detecting faults during scan testing

IC test circuitry with tri-state buffer, comparator, and scan cell

Integrated circuit with plural comparators receiving expected data and mask data from different pads

Optimization of a storage system containing ECC and scramble engines

Scan chain masking qualification circuit shift register and bit-field decoders

Three-dimensional processing system having at least one layer with circuitry dedicated to scan testing and system state checkpointing of other system layers

Fault-driven scan chain configuration for test-per-clock

IC with connections between linking module and test access ports

I/O circuitry free of test clock coupled with destination/source circuitry

Managing redundancy repair using boundary scans

Scheme for masking output of scan chains in test circuit

SCANNABLE SEQUENTIAL ELEMENTS

Core circuitry, test access mechanism, scan frame input register, decompressor

Semiconductor device, physical quantity sensor, electronic apparatus, and moving object

Vehicle measurement apparatus having a system-on-a-chip device and a sensor

Parallel scan paths with three bond pads, distributors and collectors

At-speed scan testing of clock divider logic in a clock module of an integrated circuit

Scan circuit, semiconductor device, and method for testing semiconductor device

SERIAL I/O USING JTAG TCK AND TMS SIGNALS

Semiconductor test system and method

JTAG multiplexer with clock/mode input, mode/clock input and mode output

On-chip controller and a system-on-chip

Dynamic design partitioning for scan chain diagnosis

Testing apparatus and testing method of electronic device

IC linking module gating inputs of TAP select and enable

Test access port and TMS communication circuitry with state machines

Circuitry selectively coupling scan circuitry to test data out lead

Flip-flop circuit having a reduced hold time requirement for a scan input

SCAN CLOCK GENERATOR AND RELATED METHOD THEREOF

Blocking the effects of scan chain testing upon a change in scan chain topology

Efficient scan latch systems and methods

Scan chain fault diagnosis

CIRCUITS AND METHODS FOR FUNCTIONAL TESTING OF INTEGRATED CIRCUIT CHIPS

Translating operate state into operate scan paths, A, B, C

Path-based crosstalk fault test scanning in built-in self-testing

Gating WSP capture and TAP ShiftDR with TAP IR enable

Scan test controller with state machine and gates

Circuit and method for diagnosing scan chain failures

Clock and mode signals for header and data communications

Data, mode and ready bit packets on bidirectional control/data leads

Multiplexer coupled to second core output and first core input

System and method for performing scan test

Scan test circuitry configured to prevent capture of potentially non-deterministic values

Operating scan path generators and compactors sequentially and capturing simultaneously

Base, IC, and coupling interposer with boundary scan register

JTAG-based programming and debug

Method for designing semiconductor integrated circuit

Integrated circuits capable of generating test mode control signals for scan tests

Formatter selectively routing response data to stimulus data inputs

Semiconductor device

SCAN-BASED CAPTURE AND SHIFT OF INTERFACE FUNCTIONAL SIGNAL VALUES IN CONJUNCTION WITH BUILT-IN SELF-TEST

Optimized synchronous scan flip flop circuit

System for testing electronic circuits

Scan test circuitry configured for bypassing selected segments of a multi-segment scan chain

Scan test circuitry with delay defect bypass functionality

Device and method for selective reduced power mode in volatile memory units

Asynchronous memory element for scanning

Memory hard macro partition optimization for testing embedded memories

Test access and scan test ports with lockout signal terminal

Scan chain fault diagnosis

Selection circuit with only idel, capture, shift, and update states

Built-in self-test for interposer

Parallel scan paths with three bond pads, distributors and collectors

Data source, destination and input/output circuit with multiplexer and flip-flop

Method for partitioning scan chain

IC TAP with IR select output and controller enable input

IC dies with serarate connections to expected and mask data

Efficient wrapper cell design for scan testing of integrated

Parallel scan paths with stimulus and header data circuitry

Scan collector and parallel scan paths with controlled output buffer

Semiconductor device

Taps with link update, data, instruction, and augmentation registers

Logic 1 and 0 formatter inputs for parallel scan paths

Generator/compactor scan circuit low power adaptor with state machine

TDI multiplexer gating controlled by override selection logic

IR output of mode-1 and ATC enable; ATC gating of shift-1

Semiconductor device, and test method for same

Interposer having functional leads, TAP, trigger unit, and monitor circuitry

Circuit and method for diagnosing scan chain failures

Tap time division multiplexing with scan test

I/O and comparator circuitry with compare gate and mask circuitry

Semiconductor integrated circuit and method for designing the same

Method and apparatus for fault injection

Two-dimensional scan architecture

IC clock doubler output gated to multiplexer and output buffer

Bi-directional TMS lead carrying TMS and frame data in/out signals

Boundary scan paths with shared scan cells and resynchronization memories

Interposer TAP boundary register coupling stacked die functional input/output data

Scan distributor and parallel scan paths with controlled output buffer

TAP and AUX with IR control of TDI input multiplexer

Data register control from TAP+ATC or discrete WSP signals

Driving circuit of a test access port

Adapter leads connected to test circuitry and third leads set

TAP with serial I/O coupled to TCK

Avoiding BIST and MBIST intrusion logic in critical timing paths

Configurable Mux-D scan flip-flop design

Method and system for providing efficient on-product clock generation for domains compatible with compression

Tap and scan test port with IR lock out output

Multiplexer with serial and scan data inputs for scan path

Selection circuit enabling clock/mode or mode/clock signals

Multiplexer for tap controller and WSP controller outputs

Circuit for testing integrated circuits

Scan paths, stimulus, and header circuitry with command/frame marker outputs

Masking circuit removing unknown bit from cell in scan chain

Pass/fail scan memory with AND, OR and trinary gates

Operating scan paths sequentially and capturing simultaneously

IC with test and shadow access ports and output circuit

Logic applying serial test bits to scan paths in parallel

Receiving control signals and operating separate scan paths with adaptor

Test architecture including cyclical cache chains, selective bypass scan chain segments, and blocking circuitry

Testing system for integrated circuits including components for receiving clock signals corresponding to different clock domains

TAM with scan frame copy register coupled with serial output

Verification of design information for controlling manufacture of a system on a chip

Selectively accessing test access ports in a multiple test access port environment

State machine select inputs coupled to TDI, TCK, and TMS

Position independent testing of circuits

Selectively accessing test access ports in a multiple test access port environment

Selectively accessing test access ports in a multiple test access port environment

Linking module enable leads connected to plural TAPs

Linking module connected to select leads of plural TAPs

Instruction register delay select outputs to clock delay circuitry

Resynchronization memory in series/parallel with control/output data scan cells

Adapting scan-BIST architectures for low power operation

TAP linking module TDI multiplexer circuitry to plural TAPs

Data register control of TDI/AX1 to the data register

Gates and sync circuitry connecting TAP to serial communications circuitry

Adaptor With Clocks For Like Parts of Different Scan Paths

Resynchronization memory in series/parallel with control/data scan cells

BDX DATA IN STABLE STATES

IC with first and second distributors collectors and scan paths

System and method for single terminal boundary scan

IEEE 1149.1 and P1500 test interfaces combined circuits and processes

Source and destination data circuitry coupled to bi-directional TMS lead

Multiplexer selecting STP clock signal with tap control outputs

Logic applying different bit positions to respective scan paths

Clock and mode signals controlling data communication in three states

Shift register circuit

Comparator receiving expected and mask data from circuit pads

Multi-mode programmable scan flop

Scan testable register file

Comparing supplied and sampled link ID bits on TMS lead

Effecting adapter commands upon sequential target system TAP states

TAP with enable input gated and multiplexed mode select

TAP with select output from one of IR and DR

Selectively accessing test access ports in a multiple test access port environment

Analog scan circuit, analog flip-flop, and data processing apparatus

System and method for testing a circuit

SEMICONDUCTOR INTEGRATED CIRCUIT, INFORMATION PROCESSING APPARATUS, OUTPUT DATA DIFFUSION METHOD, AND PROGRAM

Register selection circuitry receiving select signals from test interfaces

Compressing test responses using a compactor

BDX data in stable states

Wrapper leads gating TAP instruction and data registers

IEEE 1149.1 and P1500 test interfaces combined circuits and processes

EMBEDDED TEST SYSTEM AND METHOD

JTAG bus communication method and apparatus

JTAG debug test system adapter with three sets of leads

Generator/compactor scan circuit low power adapter

Dynamically reconfigurable shared scan-in test architecture

Secure scan design

Boundary scan path method and system with functional and non-functional scan cell memories

Dual mode test access port method and apparatus

Plural circuit selection using role reversing control inputs

Tap time division multiplexing with scan test

Systems and methods of implementing remote boundary scan features

Multiplexer connecting TDI or AX1/TDI to data and instruction registers

Augmentation instruction shift register with serial and two parallel inputs

Sequential element low power scan implementation

Serial I/O using JTAG TCK and TMS signals

TAP sampling at double rate

Formatter selectively outputting scan stimulus data from scan response data

SYSTEM AND METHOD FOR TESTING APPLICATION-SPECIFIC BLOCKS EMBEDDED IN RECONFIGURABLE ARRAYS

Parallel scan distributors and collectors and process of testing integrated circuits

Parallel scan distributors and collectors and process of testing integrated circuits

Parallel scan distributors and collectors and process of testing integrated circuits

Clock delay circuits and multiplexer connected to boundary scan circuitry

Parallel scan distributors and collectors and process of testing integrated circuits

Scan controller control input to sequential core without scan path

TAM with scan frame copy register coupled with serial output

IC with comparator receiving expected and mask data from pads

Implementing isolation of VLSI scan chain using ABIST test patterns

Scan path adaptor with state machine, counter, and gate circuitry

Semiconductor integrated circuit and testing method therefor

System and method for power reduction through power aware latch weighting of complex sub-circuits

Thin film magnetic head having a pair of magnetic layers whose magnetization is controlled by shield layers

IEEE 1149.1 and P1500 test interfaces combined circuits and processes

Dynamically reconfigurable shared scan-in test architecture

Selectively accessing test access ports in a multiple test access port environment

Dynamically reconfigurable shared scan-in test architecture

Providing trusted access to a JTAG scan interface in a microprocessor

Method and apparatus for securing digital information on an integrated circuit read only memory during test operating modes

Parallel scan paths with header data circuitry and header return circuitry

Dynamically reconfigurable shared scan-in test architecture

SEMICONDUCTOR DEVICES, INTEGRATED CIRCUIT PACKAGES AND TESTING METHODS THEREOF

Mode selection based on special sequence of state machine states

Boundary scan path method and system with functional and non-functional scan cell memories

Fault diagnosis of compressed test responses

TAP and shadow port operating on rising and falling TCK

Method for race prevention and a device having race prevention capabilities

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

METHOD FOR PERFORMING LOGIC BUILT-IN-SELF-TEST CYCLES ON A SEMICONDUCTOR CHIP AND A CORRESPONDING SEMICONDUCTOR CHIP WITH A TEST ENGINE

System and method for sharing a communications link between multiple communications protocols

Plural circuit selection using role reversing control inputs

Diagnosable general purpose test registers scan chain design

Method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy

Automated system and processing for expedient diagnosis of broken shift registers latch chains

Apparatus and method for controlling dynamic modification of a scan path

Apparatus and method for isolating portions of a scan path of a system-on-chip

Test access mechanism for multi-core processor or other integrated circuit

BIST scan path parts with test generator and compactor circuitry

Method of stitching scan flipflops together to form a scan chain with a reduced wire length

Method and apparatus for on-the-fly minimum power state transition

INTEGRATED CIRCUITS HAVING DEVICES IN ADJACENT STANDARD CELLS COUPLED BY THE GATE ELECTRODE LAYER

Protecting an integrated circuit test mode

Position independent testing of circuits

Boundary scan method, system and device

System and method for scanning sequential logic elements

Analog IC having test arrangement and test method for such an IC

Scan-load-based dynamic scan configuration

Scan output connection in tap and scan test port

Adapting scan architectures for low power operation

JTAG bus communication method and apparatus

Propagation test strobe circuitry with boundary scan circuitry

Methods for analyzing scan chains, and for determining numbers or locations of hold time faults in scan chains

SYSTEM AND METHOD FOR CONDITIONING AND IDENTIFYING BAD BLOCKS IN INTEGRATED CIRCUITS

Semiconductor integrated circuit

Semiconductor test system and test method thereof

IC with comparator receiving expected and mask data from pads

Scan test circuit

Parallel scan distributors and collectors and process of testing integrated circuits

Parallel scan distributors and collectors and process of testing integrated circuits

Parallel scan distributors and collectors and process of testing integrated circuits

Cell with fixed output voltage for integrated circuit

Scan path circuit and semiconductor integrated circuit

Device for thorough testing of secure electronic components

Select signal and component override signal controlling multiplexing TDI/TDO

Multiple uses for BIST test latches

TRADING PROPENSITY-BASED CLUSTERING OF CIRCUIT ELEMENTS IN A CIRCUIT DESIGN

Dynamically reconfigurable shared scan-in test architecture

Dynamically reconfigurable shared scan-in test architecture

System and methods of balancing scan chains and inserting the balanced-length scan chains into hierarchically designed integrated circuits

JTAG test architecture for multi-chip pack

Network core access architecture

Scan flip-flop with internal latency for scan input

Testing Using Independently Controllable Voltage Islands

SINGLE SCAN CLOCK IN A MULTI-CLOCK DOMAIN

Plural circuit selection using role reversing control inputs

Intergrated circuit self-test architecture

TEST STANDARD INTERFACES AND ARCHITECTURES

IC testing methods and apparatus

Circuit state scan-chain, data collection system and emulation and verification method

IEEE 1149.1 and P1500 test interfaces combined circuits and processes

Boundary scan path method and system with functional and non-functional scan cell memories

Serial I/O using JTAG TCK and TMS signals

Sharing routing of a test signal with an alternative power supply to combinatorial logic for low power design

Testing A Pipeline In An Ic

Wireless-interface module and electronic apparatus

Integrated circuit, system and method including a performance test mode

Methods for forming area-efficient scan chains in integrated circuits, and integrated circuits embodying the same

Integrated circuit and the corresponding test method, computer device and program

Integrated circuit having configurable cells and a secured test mode

SYSTEM AND APPARATUS FOR IMPROVING LOGICAL BUILT-IN SELF TEST (LBIST) AC FAULT ISOLATIONS

Direct scan access JTAG

Method and system for protecting processors from unauthorized debug access

Scan distributor loading scan paths simultaneous with loading test data

Method, apparatus and computer program product for implementing scan-chain-specific control signals as part of a scan chain

Method And Apparatus For Scan Chain Circuit AC Test

Compressing test responses using a compactor

Method and system for designing test circuit in a system on chip

System and method for testing state retention circuits

IC with comparator receiving expected and mask data from pads

Semiconductor integrated circuit and control method thereof

Single event upset test circuit and methodology

Analyzer

Modifying a test pattern to control power supply noise

JTAG boundary scan compliant testing architecture with full and partial disable

Sequential Scan Technique Providing Reliable Testing of an Integrated Circuit

Select and enable leads connecting IC taps and embedded controller

SCAN CHAIN IN A CUSTOM ELECTRONIC CIRCUIT DESIGN

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

System and method for reducing test time for loading and executing an architecture verification program for a SoC

Full scan solution for latched-based design

SCAN CHAIN CIRCUITRY THAT ENABLES SCAN TESTING AT FUNCTIONAL CLOCK SPEED

JTAG circuit transferring data between devices on TCK terminals

Circuits with state circuitry having cross connected control inputs

Propagation test strobe circuitry with boundary scan circuitry

Device test apparatus