SCAN CHAIN SEGMENTATION FOR AN INTEGRATED CIRCUIT

SYSTEMS AND METHODS FOR SCAN CHAIN INTERFACE FOR NON-VOLATILE STORAGE BITS

Scan Chain Analysis Using Predefined Capture Signature

EFFICIENT AND HIGH COVERAGE TESTING APPROACH FOR MEMORY DEVICES

SCAN TEST CIRCUIT

Scan Test Security for Semiconductor Devices

FLIP-FLOPS FOR CIRCUIT TESTING BASED ON SCAN CHAINS

LOGIC BIST CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING SAME

ELECTRONIC DEVICE AND METHOD FOR RESTORING A STATE OF AN INTEGRATED CIRCUIT

SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS

CIRCUITRY INCLUDING SCAN AND NON-SCAN REGISTERS

ENCRYPTION OF SCAN CHAIN OUTPUT

LOW PIN COUNT SCAN WITH NO DEDICATED SCAN ENABLE PIN

INTERPOSER CIRCUIT

Data Gating Using Scan Enable Pin

CIRCUIT INPUT/OUTPUT (I/O) TEST SYSTEM

SCAN CHAINS WITH MULTI-BIT CELLS AND METHODS FOR TESTING THE SAME

ARCHITECTURE FOR TESTING MULTIPLE SCAN CHAINS

MODULAR SCAN DATA NETWORK FOR HIGH SPEED SCAN DATA TRANSFER

TESTING CIRCUIT

SYSTEM FOR AUTOMATED DATA RETRIEVAL FROM AN INTEGRATED CIRCUIT FOR EVENT ANALYSIS

Scan Data Transfer Circuits for Multi-die Chip Testing

BOUNDARY SCAN FOR SHARED ANALOG AND DIGITAL PINS

SCAN-SHIFT BUFFER ISOLATOR FOR DYNAMIC POWER REDUCTION

TEST-TIME OPTIMIZATION WITH FEW SLOW SCAN PADS

INTEGRATED CIRCUIT WITH MULTIPLEXER FOR TESTING

Scan chains with multi-bit cells and methods for testing the same

LOGIC BIST CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING SAME

SCAN-TESTABLE ELECTRONIC CIRCUIT AND CORRESPONDING METHOD OF TESTING AN ELECTRONIC CIRCUIT

TEST PATTERN GENERATION USING MULTIPLE SCAN ENABLES

INTEGRATED-CIRCUIT CHIP FOR RETENTION CELL TESTING

TVF TRANSITION COVERAGE WITH SELF-TEST AND PRODUCTION-TEST TIME REDUCTION

Scan chain analysis using predefined capture signature

Compression-based scan test system

CLUSTERING CLOCK CHAIN DATA FOR TEST-TIME REDUCTION

Wrapper Cell Design and Built-In Self-Test Architecture for 3DIC Test and Diagnosis

Scan Flip-Flops With Pre-Setting Combinational Logic

Segmented Boundary Scan Chain Testing

METHODS AND APPARATUS TO IDENTIFY FAULTS IN PROCESSORS

MEMORY TIMING CHARACTERIZATION CIRCUITRY

INTEGRATED CIRCUIT COMPRISING A TEST CIRCUIT, RELATED METHOD AND COMPUTER-PROGRAM PRODUCT

Methods and apparatus to implement a boundary scan for shared analog and digital pins

SCAN CHAIN SECURITY CIRCUIT AND DRIVING METHOD THEREOF

Flip-flop device and method of operating flip-flop device

AREA, COST, AND TIME-EFFECTIVE SCAN COVERAGE IMPROVEMENT

SINGLE "A" LATCH WITH AN ARRAY OF "B" LATCHES

Secured scan access for a device including a scan chain

Saving and restoring scan states

Emulation of JTAG/SCAN test interface protocols using SPI communication device

AUTOMATED TEST PATTERN GENERATION FOR TESTING DESIGN REDACTING RECONFIGURABLE HARDWARE

MULTIPLE ACCESS PORT CIRCUITS

Scan tree construction

META-STABILITY-FREE TWO-CLOCK-DOMAIN SYNCHRONOUS LATCH

SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS

INTERPOSER INSTRUMENTATION METHOD AND APPARATUS

SYSTEMS AND METHODS FOR SCAN CHAIN INTERFACE FOR NON-VOLATILE STORAGE BITS

Dynamic voltage frequency scaling to reduce test time

SECURED SCAN ACCESS FOR A DEVICE INCLUDING A SCAN CHAIN

System of performing boundary scan test on pin through test point and method thereof

Flexible one-hot decoding logic for clock controls

INTERPOSER CIRCUIT

Scan flip-flops with pre-setting combinational logic

INTEGRATED CIRCUIT PACKAGE FOR SCAN TESTING SEMICONDUCTOR CHIP, OPERATING METHOD OF INTEGRATED CIRCUIT PACKAGE, AND INTEGRATED CIRCUIT

Scan testing using scan frames with embedded commands

Registers

INTERFACE/UNICAST FOR TEST CONTENT, FIRMWARE, AND SOFTWARE DELIVERY

Using scan chains to read out data from integrated sensors during scan tests

SEMICONDUCTOR DEVICE AND SCAN TESTING METHOD

SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS

Scan compression through pin data encoding

Wrapper cell design and built-in self-test architecture for 3DIC test and diagnosis

Redundancy circuit

Methods and apparatus to identify faults in processors

Systems and methods for database scan acceleration

Test circuit and test method

Integrated circuit margin measurement for structural testing

Decompression circuit, circuit generation method, and IC chip

Scan frame based test access mechanisms

Invisible scan architecture for secure testing of digital designs

Dynamic security protection in configurable analog signal chains

Interposer circuit

Data gating using scan enable pin

Compressed scan chain diagnosis by internal chain observation, processes, circuits, devices and systems

Shadow access port method and apparatus

Server JTAG component adaptive interconnection system and method

Memory chip and memory system

Method and measurement instrument for testing a device under test

Integrated test circuit, test assembly and method for testing an integrated circuit

Automatic test pattern generation circuitry in multi power domain system on a chip

Stacked Integrated Circuit Device

Scan architecture for interconnect testing in 3D integrated circuits

Integrated circuit, an apparatus for testing an integrated circuit, a method for testing an integrated circuit and a computer program for implementing this method using magnetic field

Flip-flop device and method of operating flip-flop device

Semiconductor device and semiconductor device examination method

Integrated circuit, test assembly and method for testing an integrated circuit

Software-Defined Synthesizable Testbench

Scan testing in a processor

Data gating using scan enable pin

Single “A” latch with an array of “B” latches

Computer-readable recording medium storing analysis program, analysis method, and analysis device

Scan apparatus capable of fault diagnosis and scan chain fault diagnosis method

Reconfigurable JTAG architecture for implementation of programmable hardware security features in digital designs

Method for testing a circuit system and a circuit system thereof

Test architecture for electronic circuits, corresponding device and method

Test circuit

Interposer instrumentation method and apparatus

Chip, chip testing method and electronic device

Circuits And Methods For Configurable Scan Chains

Method and apparatus for debugging integrated circuit systems using scan chain

Scan frame based test access mechanisms

Method and circuit for scan dump of latch array

Method and circuit for row scannable latch array

Direct scan access JTAG

Test access port architecture to facilitate multiple testing modes

Extended JTAG controller and method for functional debugging using the extended JTAG controller

Techniques for isolating interfaces while testing semiconductor devices

Self-test circuit for an integrated circuit, and method for operating a self-test circuit for an integrated circuit

Circuit and testing circuit thereof

Suspect resolution for scan chain defect diagnosis

Method for allocating addresses and corresponding units

Bidirectional scan cells for single-path reversible scan chains

Debug support device, debug support method, and computer readable storage medium

IEEE 1149.1 interposer apparatus

Scan testing using scan frames with embedded commands

Shadow access port integrated circuit

FLEXIBLE INTERFACE

Deterministic stellar built-in self test

Compressed scan chain diagnosis by internal chain observation, processes, circuits, devices and systems

Switch-Mode Based Interposer Enabling Self-Testing Of An MCM Without Known Good Die

Asynchronous circuits and test methods

Flip-flop device and method of operating flip-flop device

Phase controlled codec block scan of a partitioned circuit device

Systems and methods for testing many-core processors

Integrated circuit with self-test circuit, method for operating an integrated circuit with self-test circuit, multi-core processor device and method for operating a multi-core processor device

Semiconductor integrated circuit having scan chains sequentially supplied with a clock signal

Electronic circuit and corresponding method of testing electronic circuits

Flip-flop device and method of operating flip-flop device

JTAG bus communication method and apparatus

Full pad coverage boundary scan

Double edge triggered Mux-D scan flip-flop

Interposer instrumentation method and apparatus

Dynamic security protection in configurable analog signal chains

Trajectory-optimized test pattern generation for built-in self-test

Test method and test system

Test access port architecture to facilitate multiple testing modes

Semiconductor device

Reversible multi-bit scan cell-based scan chains for improving chain diagnostic resolution

Flexible isometric decompressor architecture for test compression

Phase controlled codec block scan of a partitioned circuit device

Test circuit for dynamic checking for faults on functional and BIST clock paths to memory in both ATPG and LBIST modes

Dynamic security protection in configurable analog signal chains

IC analog boundary scan cell, digital cell, comparator, analog switches

Power-aware scan partitioning

Semiconductor integrated circuit

CIRCUITRY DESIGN METHOD AND STORAGE MEDIUM

Method for reducing power consumption in scannable flip-flops without additional circuitry

Direct scan access JTAG

Scan frame based test access mechanisms

Test access port architecture to facilitate multiple testing modes

TAP,TCK inverter,shadow access port scan/instruction registers,state machine

Stacked die interposer monitor trigger, address comparator, trigger controller circuitry

Circuit having multiple scan modes for testing

Test system with embedded tester

Functional circuitry, decompressor circuitry, scan circuitry, masking circuitry, qualification circuitry

IC test architecture having differential data input and output buffers

Scan chain techniques and method of using scan chain structure

Asynchronous circuits and test methods

Scan architecture for interconnect testing in 3D integrated circuits

Serial data communication modes on TDI/TDO, receive TMS, send TMS

Intrusion detection for integrated circuits

Secure debug system for electronic devices

Memory loopback systems and methods

Boundary scan and wrapper circuitry with state machine and multiplexers

SEMICONDUCTOR DEVICE, SEMICONDUCTOR DESIGNING DEVICE, AND SEMICONDUCTOR TEST DEVICE

Isometric control data generation for test compression

Full pad coverage boundary scan

Interposer analog scan with digital scan cell, comparator, analog switches

Tap, counter storing value of serial access by communication circuitry

System For Using Different Scan Chains To Test Differential Circuit, And Method Thereof

Scan frame input register to decompressor parallel scan path outputs

Test access port, test clock inverter, and shadow access port

Broadcast scan network

Method to sort partially good cores for specific operating system usage

Method for identifying a fault at a device output and system therefor

Systems and methods for bypass testing

Power-aware scan partitioning

Regulator control during scan shift and capture cycles

Wrapper serial port externally accessible pin providing additional tap control

Signals on tap bi-directional TMS terminal selecting serial communication register

Memory loopback systems and methods

Core circuitry, tap domain circuitry, separate auxiliary circuitry, output buffers

Register array having groups of latches with single test latch testable in single pass

Input shift register having parallel serial scan outputs, command output

Interposer monitor, monitor trigger circuitry having select output and input

Efficient test architecture for multi-die chips

IC TAP, SAP state machine stepping on TCK falling edge

Dynamic scan chain reconfiguration in an integrated circuit

Semiconductor integrated circuit and semiconductor integrated circuit diagnosis method

Semiconductor circuit

Compressed scan chains with three input mask gates and registers

CLOCK GATING CIRCUITS AND SCAN CHAIN CIRCUITS USING THE SAME

Scan cell for dual port memory applications

Internal circuit TMS input, FIFO coupled to parallel-input serial-output register

TMS pin for mode signal and output for read data

Scan path only one-bit scan register when component not selected

Interface circuit for scan paths providing separate multiplexer controls

Sequential circuit, scan chain circuit including the same and integrated circuit including the same

Serial communication control

Integrated electronic device having a test architecture, and test method thereof

Functional core circuitry with serial scan test expected, mask circuitry

Apparatus, method, and system for testing IC chip

Full pad coverage boundary scan

Integrated circuit automatic test system and integrated circuit automatic test method storing test data in scan chains

Circuit and method for diagnosing scan chain failures

TAP and gating enable, CaptureDR, capture, and gated CaptureDR signals

Logic built-in self-test (LBIST) with pipeline scan enable launch on shift (LOS) flip-flop circuit

Semiconductor device, electronic device, and self-diagnosis method for semiconductor device

Mixed-signal integrated circuit

Tap and auxiliary circuitry with auxiliary output multiplexer and buffers

Full pad coverage boundary scan

Analog input digital boundary scan cell, comparator, and analog switches

Scan path interface with circular shift register, logic, register sets

Scan input stimulus registers, test control register controlling compressor circuitry

Differential I/O for parallel scan paths, scan frames, embedded commands

Interpose tap, Monitor trigger circuitry coupled to temperature sensor circuitry

First, second divided scan paths, adaptor, generator and compactor circuitry

Test access port and TCK inverter for shadow access port

Cores with separate serial scan paths and scan path parts

Efficient scan latch systems and methods

Scan test circuit, scan test method, and method of designing scan test circuit

Status register between test data I/O of scan port SUT

Scan chain circuits in non-volatile memory

On-chip test pattern generation

IC expected data and mask data on I/O data pads

Integrated circuit with secure scan enable

Gating tap register control bus and auxiliary/wrapper test bus

High speed interconnect circuit test method and apparatus

TAP and auxiliary circuitry with auxiliary output multiplexer and buffers

TMS serial communication circuitry coupled to tap IR enable output

Selectable separate scan paths with hold state multiplexer and adapter

Low power scan path cells with hold state multiplexer circuitry

Interface with write strobe sequencer, first and second series registers

Scan testing scan frames with embedded commands and differential signaling

IC interposer with TAP controller and output boundary scan cell

Integrated electronic device having a test architecture, and test method thereof

Bypass register separately controlled as internal scan circuit by TAP

Blocking the effects of scan chain testing upon a change in scan chain topology

Semiconductor device, electronic device, and self-diagnosis method for semiconductor device

Method and system for digital circuit scan testing

Tap decay test circuitry having capture test strobe enable input

TAP gated updateDR output AUX test control of WSP update

Embedded parallel scan paths, stimulus formatter, and control interface circuitry

Three-dimensional processing system having at least one layer with circuitry dedicated to scan testing and system state checkpointing of other system layers

Semiconductor device, physical quantity sensor, electronic apparatus, and moving object

Integrated circuit wafer having plural dies with each die including test circuit receiving expected data and mask data from different pads

IC decompress and maskable compress TAM with SFIR and SFCR

Parallel and serial data with controller, delay, and register circuits

Blocking the effects of scan chain testing upon a change in scan chain topology

Circuit for testing integrated circuits

Interposer with TAP, trigger, address/data bus, and analog monitor circuitry

Transporting ordered test data, mode select, ready, precharge packet bits

Compressed scan chains with three input mask gates and registers

IC output circuit with test data and shadow data inputs

Semiconductor test system and method

Integrated circuit device and method of performing self-testing within an integrated circuit device

Circuit and method for diagnosing scan chain failures

Test clock/test mode slect (TCK/TMS), select, data register (DR) connection circuitry between test access port (TAP) and bypass register

Logic-built-in-self-test diagnostic method for root cause identification

Logic-built-in-self-test diagnostic method for root cause identification

Scan test multiplexing

Scan test multiplexing

Blocking the effects of scan chain testing upon a change in scan chain topology

IR enabled gating of TAP and WSP shift, capture, transfer

Tap and aux circuitry with multiplexers on TDI, TDO, AUXI/O

Divided scan path cells with first and state hold multiplexers

Managing redundancy repair using boundary scans

Bi-directional TCK lead carrying TCK and frame data in/out signal

Electronic device and method for state retention

Scan response reuse method and apparatus

Method and apparatus for scan chain data management

At-speed test of memory arrays using scan

Semiconductor test system and method

TAP with AUX capture input, gated capture and shiftDR outputs

Integrated circuit wafer having integrated circuit die with plural comparators receiving expected data and mask data from different pads

Low power Scan-BIST test data generator and compactor pass/fail output

Reset scheme for scan chains with asynchronous reset signals

Gated state machine circuitry having three clock 2 enable states

Decompressed scan chain masking circuit shift register with log2(n/n) cells

Method and apparatus for at-speed scan shift frequency test optimization

Serial input/output, source/destination bus data multiplexer, flip flop, and controller circuitry

Blocking the effects of scan chain testing upon a change in scan chain topology

Boundary control scan cells, data cells, resynchronization memories, and multiplexers

IC test circuitry and adapter with data transport control register

DFT approach to enable faster scan chain diagnosis

Semiconductor test system and method

Semiconductor chip, stack chip including the same, and testing method thereof

IC tap/scan selecting between TDI/SI and a test pattern source

Interposer capture shift update cell between functional and test data

Dynamic shift for test pattern compression

Tap and shadow access port output circuitry with clock doubler