171895 ⎘
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere; Testing of electronic circuits, e.g. by signal tracer; Testing of digital circuits; Functional testing; Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG Input/Output interfaces
Taps and hierarchical TLM with shift register, and state machine
#302Interface device and method
#303SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT
#304Scan distributor and parallel scan paths with controlled output buffer
#305TAP and AUX with IR control of TDI input multiplexer
#306TEST ACCESS PORT WITH ADDRESS AND COMMAND CAPABILITY
#307Multiplexer control circuitry for TAP selection circuitry
#308AT-SPEED SCAN ENABLE SWITCHING CIRCUIT
#309Digital circuit testable through two pins
#310Driving circuit of a test access port
#311Adapter leads connected to test circuitry and third leads set
#312Feedback scan isolation and scan bypass architecture
#313Detecting an unstable input to an IC
#314Scan path switch testing of output buffer with ESD
#315Apparatus and method for testing driver writeability strength on an integrated circuit
#316Method and apparatus for testing 3D integrated circuits
#317AT speed TAP with dual port router and command circuit
#318Tap and scan test port with IR lock out output
#319State machine transitioning from sequence 1 to sequence 2 to idle 2
#320Latching control buffer between functional logic and tri-state output buffer
#321Circuit for testing integrated circuits
#322Device address port circuitry with local, group, and global outputs
#323On-chip service processor
#324Method and apparatus for providing scan chain security
#325Scan paths, stimulus, and header circuitry with command/frame marker outputs
#326SEMICONDUCTOR DEVICE COMPRISING SHIELD TREE AND RELATED LAYOUT METHOD
#327Remote testing system
#328Pass/fail scan memory with AND, OR and trinary gates
#329Clock controller for JTAG interface
#330Semiconductor device having input/output wrappers, and a method of controlling the wrappers
#331Target device providing debugging function and test system comprising the same
#332Die with DIO path, clock input, TLM, and TAP domains
#333Multiplexer Control Circuitry for TAP Domain Selection Circuitry
#334Terminal discriminating apparatus and terminal discriminating method using the same
#335Data recirculation in configured scan paths
#336HTMLS with first and second select outputs and enable inputs
#337Selectively accessing test access ports in a multiple test access port environment
#338State machine select inputs coupled to TDI, TCK, and TMS
#339Position independent testing of circuits
#340Selectively accessing test access ports in a multiple test access port environment
#341Selectively accessing test access ports in a multiple test access port environment
#342Linking module enable leads connected to plural TAPs
#343Linking module connected to select leads of plural TAPs
#344Instruction register delay select outputs to clock delay circuitry
#345Test access port with address and command capability
#346Transitioning through idle 1, 2 and sequence 1 machine states
#347Process for making an electric testing of electronic devices
#348CONTROLLING TWO JTAG TAP CONTROLLERS WITH ONE SET OF JTAG PINS
#349IC OUTPUT SIGNAL PATH WITH SWITCH, BUS HOLDER, AND BUFFER
#350Input buffer, test switches and switch control with serial I/O
#351Data register control of TDI/AX1 to the data register
#352Testing circuit and method
#353Interface logic for a multi-core system-on-a-chip (SoC)
#354IC with TAP, DIO interface, SIPE, and PISO circuits
#355Semiconductor device test system with test interface means
#356Tap and control with data I/O, TMS, TDI, and TDO
#357System and method for single terminal boundary scan
#358Multiplexer selecting STP clock signal with tap control outputs
#359Communication between controller and addressed target devices over data signal
#360IC output signal path with switch, bus holder, and buffer
#361Comparator receiving expected and mask data from circuit pads
#362Optimized JTAG interface
#363Method and apparatus for interrogating electronic equipment components
#364Scan testable register file
#365Apparatus and method for testing level shifter voltage thresholds on an integrated circuit
#366Apparatus and method for testing driver writeability strength on an integrated circuit
#367TAP with enable input gated and multiplexed mode select
#368TAP with select output from one of IR and DR
#369Wafer scale testing using a 2 signal JTAG interface
#370Selectively accessing test access ports in a multiple test access port environment
#371Debugging module for electronic device and method thereof
#372Method for carrying out bidirectional communications
#373Method and apparatus for virtual in-circuit emulation
#374IC multiplexer control circuitry for tap selection circuitry
#375TAP state count specifying advanced mode command and command data
#376Tap demultiplexer with select and select one outputs for HTML
#377Techniques for boundary scan testing using transmitters and receivers
#378Selectable JTAG or trace access with data store and output
#379Register selection circuitry receiving select signals from test interfaces
#380JTAG mailbox
#381TESTABLE INTEGRATED CIRCUIT AND IC TEST METHOD
#382JTAG debug test system adapter with three sets of leads
#383Diagnostic mode switching
#384Dynamically reconfigurable shared scan-in test architecture
#385Dual mode test access port method and apparatus
#386Selecting scan test/TAP with FF receiving lock in and update-IR
#387Asynchronous Scan Chain Circuit
#388IC output signal path with switch, bus holder, and buffer
#389Multiplexer connecting TDI or AX1/TDI to data and instruction registers
#390On-chip service processor
#391Gating TDO from plural JTAG circuits
#392Clock delay circuits and multiplexer connected to boundary scan circuitry
#393Optimized JTAG interface
#394Scan controller control input to sequential core without scan path
#395IC with comparator receiving expected and mask data from pads
#396Dynamically reconfigurable shared scan-in test architecture
#397Selectively accessing test access ports in a multiple test access port environment
#398Removeable and replaceable tap domain selection circuitry
#399Dynamically reconfigurable shared scan-in test architecture
#400Parallel scan paths with header data circuitry and header return circuitry
#401Scan driver
#402Dynamically reconfigurable shared scan-in test architecture
#403Scan circuitry controlled switch connecting buffer output to test lead
#404Selectable JTAG or trace access with data store and output
#405Compressor/decompressor circuits coupled with TDO-TMS/TDI die channel circuitry
#406Identification of board connections for differential receivers
#407TAP with control circuitry connected to device address port
#408BSC macrostructure for three-dimensional wiring and substrate having the BSC macrostructure
#409Low pin interface testing module
#410System and method for sharing a communications link between multiple communications protocols
#411Structure For An Integrated Circuit That Employs Multiple Interfaces
#412Selectable dual mode test access port method and apparatus
#413Utilizing serializer-deserializer transmit and receive pads for parallel scan test data
#414Multi-chip digital system having a plurality of controllers with self-identifying signal
#415Integrated circuit with input and/or output bolton pads with integrated logic
#416Test access mechanism for multi-core processor or other integrated circuit
#417Apparatus and method for connection test on printed circuit board
#418System and method for input/output characterization
#419Position independent testing of circuits
#420Test circuit capable of sequentially performing boundary scan test and test method thereof
#421Boundary scan method, system and device
#422Scan output connection in tap and scan test port
#423MULTIPLEXING OF SCAN INPUTS AND SCAN OUTPUTS ON TEST PINS FOR TESTING OF AN INTEGRATED CIRCUIT
#424Propagation test strobe circuitry with boundary scan circuitry
#425IC output signal path with switch, bus holder, and buffer
#426Microelectronic device and pin arrangement method thereof
#427Semiconductor integrated circuit
#428IC with comparator receiving expected and mask data from pads
#429Method and apparatus for interrogating an electronic component
#430Cell with fixed output voltage for integrated circuit
#431Methodology and system to set JTAG interface
#432Three boundary scan cell switches controlling input to output buffer
#433Semiconductor integrated circuit device
#434IC CIRCUIT WITH TEST ACCESS CONTROL CIRCUIT USING A JTAG INTERFACE
#435Select signal and component override signal controlling multiplexing TDI/TDO
#436Control apparatus
#437Dynamically reconfigurable shared scan-in test architecture
#438Dynamically reconfigurable shared scan-in test architecture
#439Optimized JTAG interface
#440Probeless testing of pad buffers on wafer
#441JTAG interface
#442Address and TMS gating circuitry for TAP control circuit
#443Wafer scale testing using a 2 signal JTAG interface
#444Device and method for configuring input/output pads
#445Removable and replaceable tap domain selection circuitry
#446Communications System for Implementation of Synchronous, Multichannel, Galvanically Isolated Instrumentation Devices
#447Method to improve isolation of an open net fault in an interposer mounted module
#448Direct scan access JTAG
#449On-chip service processor
#450Scanning Latches Using Selecting Array
#451METHOD AND APPARATUS FOR INTERFACING TO AN INTEGRATED CIRCUIT THAT EMPLOYS MULTIPLE INTERFACES
#452Scanning Latches Using Selecting Array
#453Method and apparatus for limiting power dissipation in test
#454Pad unit having a test logic circuit and method of driving a system including the same
#455Middlesoft commander
#456Integrated circuit device and electronic instrument
#457Device for Measurement and Analysis of Electrical Signals of an Integrated Circuit Component
#458IC with comparator receiving expected and mask data from pads
#459Scan Testing Interface
#460Chip testing device and system
#461Select and enable leads connecting IC taps and embedded controller
#462METHODS AND APPARATUS FOR TESTING AN IC USING A PLURALITY OF I/O LINES
#463Signal output circuit, and test apparatus
#464Testing components of I/O paths of an integrated circuit
#465Propagation test strobe circuitry with boundary scan circuitry
#466Selecting between tap/scan with instructions and lock out signal
#467TAP, ST, lockout, and IR SO enable output data control
#468Generating scan test vectors for proprietary cores using pseudo pins
#469Semiconductor device testing
#470Standard cell for a CAD system
#471Systems and methods for improved fault coverage of LBIST testing
#472Test access port switch
#473Minimizing timing skew among chip level outputs for registered output signals
#474Input/output buffer test circuitry and leads additional to boundary scan
#475Scan testing using scan frames with embedded commands
#476Test access control for plural processors of an integrated circuit
#477Two boundary scan cell switches controlling input to output buffer
#478Dual-path, multimode sequential storage element
#479Hardware enablement using an interface
#480Boundary-scan system architecture for remote environmental testing
#481Sequential scan technique providing enhanced fault coverage in an integrated circuit
#482Diagnostic mode switching
#483Semiconductor device testing
#484Accelerated scan circuitry and method for reducing scan test data volume and execution time
#485Semiconductor device testing
#486Testing combinational logic die with bidirectional TDI-TMS/TDO chanel circuit
#487Comparator circuitry connected to input and output of tristate buffer
#488Remove signal from TAP selection circuitry to multiplexer control circuitry
#489Separate scan cell in series with TAP instruction register
#490SCAN TESTING SYSTEM, METHOD AND APPARATUS
#491Semiconductor device, test system and method of testing on die termination circuit
#492Serial data input/output method and apparatus
#493PC-connectivity for on-chip memory
#494In-circuit testing system and method
#495Linking addressable shadow port and protocol for serial bus networks
#496Path data transmission unit
#497Semiconductor device with test interface
#498Selectable JTAG or trace access with data store and output
#499Semiconductor device test system with test interface means
#500Fault diagnosis apparatus and method for system-on-chip (SoC) and SoC in which fault is capable of being diagnosed
#501Scan friendly domino exit and domino entry sequential circuits
#502Apparatus and method for a single wire interface between a intergated circuit and JTAG test and emulation apparatus
#503IC input memory with dual data and dual control inputs
#504Reduced-pin-count-testing architectures for applying test patterns
#505Semiconductor device and test method thereof
#506Internal core connected to bond pads by distributor and collector
#507Scan test circuit and method of arranging the same
#508Input and output circuit of an integrated circuit and a method for testing the same
#509IC with protocol selection memory coupled to serial scan path
#510AC propagation testing preventing sampling test data at Capture-DR state
#511Communication interface for diagnostic circuits of an integrated circuit
#512Controller receiving combined TMS/TDI and suppyling separate TMS and TDI
#513Debug and test system with format select register circuitry
#514JTAG testing arrangement
#515Wireless hardware debugging
#516Device for measurement and analysis of electrical signals of an integrated circuit component
#517Array self repair using built-in self test techniques
#518Boundary scan apparatus and interconnect test method
#519JTAG interface using existing I/O bus
#520Test wrapper including integrated scan chain for testing embedded hard macro in an integrated circuit chip
#521Latch circuit including a data retention latch
#522Two pin serial bus communication interface
#523Method and apparatus for an embedded time domain reflectometry test
#524Semiconductor integrated circuit device
#525Connecting multiple test access port controllers on a single test access port
#526Single pin multilevel integrated circuit test interface
#527One-hot encoded instruction register for boundary scan test compliant devices
#528On-chip service processor
#529IC with TAP, STP and lock out controlled output buffer
#530Semiconductor integrated circuit having bonding optional function
#531Semiconductor integrated circuit
#532Semiconductor device testing
#533Scanning latches using selecting array
#534System and method for front-end bypass testing in an electronic circuit
#535Semiconductor integrated circuit, checking device and method of checking semiconductor integrated circuit
#536System and scanout circuits with error resilience circuit
#537Linking addressable shadow port and protocol for serial bus networks
#538Multi-chip digital system having a plurality of controllers with input and output pins wherein self-identification signal are received and transmitted
#539Connection of auxiliary circuitry to tap and instruction register controls
#540Wrapper serial scan chain functional segmentation
#541Scan-test structure having increased effectiveness and related systems and methods
#542Dynamically reconfigurable shared scan-in test architecture
#543IC with expected data memory coupled to scan data register
#544Masking circuit and method of masking corrupted bits
#545Scan interface
#546Integrated circuit device
#547Apparatus and method for eliminating the TMS connection in a JTAG procedure
#548Apparatus and method for exchanging non-JTAG signals with a core processor during selected JTAG modes
#549Wireless no-touch testing of integrated circuits
#550IC with comparator receiving expected and mask data from pads
#551Cell with fixed output voltage for integrated circuit
#552Integrated circuit with test circuit
#553Semiconductor LSI circuit with scan circuit, scan circuit system, scanning test system and method
#554Accelerated scan circuitry and method for reducing scan test data volume and execution time
#555Removable and replaceable TAP domain selection circuitry
#556Methods and apparatus for testing an IC
#557Functional test design for testability (DFT) and test architecture for decreased tester channel resources
#558Device for measurement and analysis of electrical signals of an integrated circuit component
#559Concurrent I/O
#560Semiconductor integrated circuit device
#561Semiconductor logic circuit device having pull-up/pull-down circuit for input buffer pad and wafer-probing testing method therefor
#562Device for measurement and analysis of electrical signals of an integrated circuit component
#563Integrated circuit outputs protection during JTAG board tests
#564Method and apparatus for low overhead circuit scan
#565Programmable hysteresis for boundary-scan testing
#566Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuit
#567Semiconductor integrated circuit
#568Tap with separate scan cell in series with instruction register
#569JTAG state machines with respective enable input and select input
#570Semiconductor device test circuit and semiconductor device
#571Testing a multi-channel device
#572Accelerated scan circuitry and method for reducing scan test data volume and execution time
#573Processor interface for test access port
#574IC with protocol selection memory coupled to serial scan path
#575Electronic component with output buffer control
#576Self-test for receive and transmit hardware functional safety associated with a touch panel or screen
#577Self-correcting circuitry
#578Power-sensitive scan-chain testing
#579Hold time improved low area flip-flop architecture
#580DIMM slot test system without series connection of test board through JTAG and method thereof
#581Dummy dual in-line memory module (DIMM) testing system based on boundary scan interconnect and method thereof
#582System and method for schedule-based I/O multiplexing for integrated circuit (IC) scan test
#583Save and restore register
#584Power saving scannable latch output driver
#585Electronic device including integrated circuit with debug capabilities
#586Method for detecting faults on retention cell pins
#587Method and apparatus for scan chain reordering and optimization in physical implementation of digital integrated circuits with on-chip test compression
#588Input/output path testing and characterization using scan chains
#589Increase data transfer throughput by enabling dynamic JTAG test mode entry and sharing of all JTAG pins
#590Method for testing through silicon vias in 3D integrated circuits
#591Physically aware insertion of diagnostic circuit elements
#592Scan wrapper circuit for integrated circuit
#593Serializer/deserializer and method for transferring data between an integrated circuit and a test interface
#594System and method for providing a test result from an integrated to an analyzer
#595Clock control circuitry and methods of utilizing the clock control circuitry
#596Test access architecture for stacked memory and logic dies