SECURE SCAN TESTING OF INTEGRATED CIRCUITS

DEBUG SYSTEM AND METHOD FOR OPERATING A DEBUG SYSTEM

JTAG-BASED APPARATUS AND METHOD FOR INPUT CLOCK FREQUENCY MEASUREMENT

TEST MODE CONTROL SYSTEM AND SYSTEM-ON-CHIP INCLUDING THE SAME

PACKAGE CIRCUIT INCLUDING HOMOGENEOUS DIES

Data Gating Using Scan Enable Pin

CIRCUIT INPUT/OUTPUT (I/O) TEST SYSTEM

INTEGRATED CIRCUIT DIE TEST ARCHITECTURE

MONITOR BLOCK, INTERFACE CIRCUIT, AND METHOD OF OPERATING DEBUGGING SYSTEM

JTAG STANDARD PIN TEST SYSTEM

METHOD AND SYSTEM FOR TESTING SEMICONDUCTOR CIRCUITS

AT-SPEED TEST ACCESS PORT OPERATIONS

DESIGN FOR TEST SCANNING FOR LIGHT-EMITTING DIODE PACKAGES AND RELATED METHODS

3D TAP & SCAN PORT ARCHITECTURES

MERGED PARAMETRIC SCAN TOPOLOGY

COMMANDED JTAG TEST ACCESS PORT OPERATIONS

ERROR RATE MEASUREMENT APPARATUS AND ERROR RATE MEASUREMENT METHOD

SCAN-TESTABLE ELECTRONIC CIRCUIT AND CORRESPONDING METHOD OF TESTING AN ELECTRONIC CIRCUIT

TVF TRANSITION COVERAGE WITH SELF-TEST AND PRODUCTION-TEST TIME REDUCTION

SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT

ADDRESSABLE TEST ACCESS PORT

Wrapper Cell Design and Built-In Self-Test Architecture for 3DIC Test and Diagnosis

Segmented Boundary Scan Chain Testing

Testing system and testing method

SCAN TEST IN A SINGLE-WIRE BUS CIRCUIT

Integrated circuit die test architecture

Configurable Storage Circuits And Methods

SCAN CHAIN SECURITY CIRCUIT AND DRIVING METHOD THEREOF

Saving and restoring scan states

HOLD TIME IMPROVED LOW AREA FLIP-FLOP ARCHITECTURE

At-speed test access port operations

Performing scan data transfer inside multi-die package with serdes functionality

Cost-saving scheme for scan testing of 3D stack die

Selectable JTAG or trace access with data store and output

Scan testing using scan frames with embedded commands

Method and system for testing semiconductor circuits

3D tap and scan port architectures

INTERFACE/UNICAST FOR TEST CONTENT, FIRMWARE, AND SOFTWARE DELIVERY

Addressable test access port

Built-in self-test for die-to-die physical interfaces

SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS

MANAGING DATA PROTECTION SETTINGS FOR AN ELECTRONIC CONTROL UNIT

Wrapper cell design and built-in self-test architecture for 3DIC test and diagnosis

Integrated circuit chip testing interface with reduced signal wires

Integrated circuit die test architecture

Test access port with address and command capability

CONFIGURABLE BOUNDARY SCAN

DDR5 SDRAM DIMM slot detection system and method thereof

Process for scan chain in a memory

Stimulated circuits and fault testing methods

Commanded JTAG test access port operations

Test circuit in chip and circuit test method

Chip test circuit and circuit test method

Scan chain for memory with reduced power consumption

Data gating using scan enable pin

AT-speed test access port operations

Scan test in a single-wire bus circuit

Wafer scale testing using a 2 signal JTAG interface

3D TAP and scan port architectures

Integrated test circuit, test assembly and method for testing an integrated circuit

Stacked Integrated Circuit Device

FPGA chip with protected JTAG interface

Early detection of quality control test failures for manufacturing end-to-end testing optimization

Method for protecting a reconfigurable digital integrated circuit against reversible errors

Scan testing in a processor

Method of converting a serial vector format (SVF) file to a vector compatible with a semiconductor testing system

Data gating using scan enable pin

Apparatus and system for debugging solid-state disk (SSD) device

Memory device having an enhanced ESD protection and a secure access from a testing machine

Built-in self-test for die-to-die physical interfaces

Integrated circuit die test architecture

Electronic device comprising a memory accessible via a JTAG interface, and corresponding method of accessing a memory

Enabling isolated development mode in utility end points

METHOD AND DEVICE FOR TESTING INTEGRATED CIRCUIT

At-speed test access port operations

Circuits And Methods For Configurable Scan Chains

Systems, methods, and devices for high-speed input/output margin testing

Systems, methods, and devices for high-speed input/output margin testing

Selectable JTAG or trace access with data store and output

Direct scan access JTAG

Test access port architecture to facilitate multiple testing modes

Wafer scale testing using a 2 signal JTAG interface

3D tap and scan port architectures

Circuit and testing circuit thereof

Performing scan data transfer inside multi-die package with SERDES functionality

Test access port with address and command capability

Bidirectional scan cells for single-path reversible scan chains

Addressable test access port apparatus

MULTIPLEXER-ENABLED CABLES AND TEST FIXTURES

Scan testing using scan frames with embedded commands

FLEXIBLE INTERFACE

Two pin serial bus communication interface and process

Method of testing memory device employing limited number of test pins and memory device utilizing same

Memory device having an enhanced ESD protection and a secure access from a testing machine

Semiconductor apparatus

Integrated circuit with self-test circuit, method for operating an integrated circuit with self-test circuit, multi-core processor device and method for operating a multi-core processor device

Electronic circuit and corresponding method of testing electronic circuits

Full pad coverage boundary scan

Controller structural testing with automated test vectors

Scheme applied in JTAG TAP apparatus, JTAG host, and target system capable of achieving data verification as well as saving on-chip circuit costs

Integrated circuit die test architecture

Performing scan data transfer inside multi-die package with SERDES functionality

Method of testing memory device employing limited number of test pins and memory device utilizing same

Test access port architecture to facilitate multiple testing modes

Non-volatile computer data storage production-level programming

3D tap and scan port architectures

Tap, command, router circuitry, and data register

Wafer scale testing using a 2 signal JTAG interface

Test access port circuit capable of increasing transmission throughput

Test access port with address and command capability

Test access port with address and command capability

Scalable infield scan coverage for multi-chip module for functional safety mission application

Selectable JTAG or trace access with data store and output

CIRCUITRY DESIGN METHOD AND STORAGE MEDIUM

Direct scan access JTAG

Test access port architecture to facilitate multiple testing modes

Controller structural testing with automated test vectors

IC test architecture having differential data input and output buffers

At-speed test access port operations

Multi-stage current measurement architecture

SAS Connector Conduction Detecting System And Method Thereof

SAS Connector Conduction Detecting System And Method Thereof

Channel circuitry, tap linking module, scan tap, debug tap domains

3D tap and scan port architectures

Two die sides with PTI. PTO. TDI, TCK, TMS, TDO, PTIO contact points method

Bidirectional data pin, clock input pin, shift register, debug circuitry

Combinatorial serial and parallel test access port selection in a JTAG interface

Design-for-test for asynchronous circuit elements

Organic light emitting display device and method of manufacturing the same

Operating addressable circuit inputting separate data/address signals from data input apparatus

SEMICONDUCTOR DEVICE AND FAILURE DIAGNOSIS METHOD

Functional, tap, trace circuitry with multiplexed tap, trace data output

Full pad coverage boundary scan

IC receiving TDI addresses in R/TI after update-IR while TDI in second logic state

Up control, CSU circuit, scan circuit, up signal contact point

Wafer with dio bidirectional lead, n dies, domains, clock leads

Method for identifying a fault at a device output and system therefor

Tap, command, and router circuitry and asynchronous data register

Scalable infield scan coverage for multi-chip module for functional safety mission application

Core circuitry, tap domain circuitry, separate auxiliary circuitry, output buffers

JTAG scans through packetization

3D tap and scan port architectures

Methods and apparatus for an integrated circuit

Non-interleaved scan operation for achieving higher scan throughput in presence of slower scan outputs

Input shift register having parallel serial scan outputs, command output

Stack die gating having test control input, output, and enable

Wafer tap domain die channel circuitry with separate die clocks

Scan based test design in serdes applications

Trace domain controller with test data I/O/control, internal control I/O

Two pin serial bus communication interface

3D tap and scan port architectures

Inputting TDI addresses when TDI high, moving update-DR to RT/I

Organic light emitting display device and method of manufacturing the same

Scan path only one-bit scan register when component not selected

Two signal JTAG with TLM, scan domain and diagnostics domain

Functional core circuitry with serial scan test expected, mask circuitry

Full pad coverage boundary scan

Inverted TCK, input and fixed address registers, comparator, compare register

Logic built-in self-test (LBIST) with pipeline scan enable launch on shift (LOS) flip-flop circuit

Tap and auxiliary circuitry with auxiliary output multiplexer and buffers

One tap domain coupling two trace circuits, address command port

Dual port tap router for asynchronous capture shift data register

Differential I/O for parallel scan paths, scan frames, embedded commands

Die top, bottom parallel/serial date with test and scan circuitry

Test port, decompressor, compactor with I/O on opposite die surfaces

Method for testing through silicon vias in 3D integrated circuits

Scan chain latch design that improves testability of integrated circuits

Efficient scan latch systems and methods

Scan test circuit, scan test method, and method of designing scan test circuit

Boundary scan chain for stacked memory

IC TOP/BOTTOM SURFACES COUPLED TO TEST, SCAN, AND COMPARATOR CIRCUITRY

Status register between test data I/O of scan port SUT

Two signal JTAG wafter testing bist and scan tap domains

Testing multi-core integrated circuit with parallel scan test data inputs and outputs

Granular dynamic test systems and methods

Dynamic independent test partition clock

Scan system interface (SSI) module

Method and system for dynamic standard test access (DSTA) for a logic block reuse

Test partition external input/output interface control for test partitions in a semiconductor

IC expected data and mask data on I/O data pads

Interleaver ic with up control and capture, shift, update circuitry

High speed interconnect circuit test method and apparatus

Tap SPC with tap state machine reset and clock control

TAP and auxiliary circuitry with auxiliary output multiplexer and buffers

Organic light emitting display device and method of manufacturing the same

Address-command port connected to trace circuits and tap domains

Tap, CMD with two flip-flops, routing circuit, and data register

IC die with channel circuitry, scan and BIST taps, TLM

2-pin interface data input and output, controller and instruction circuitry

Integrated circuit and electronic apparatus including integrated circuit

DAP local, group, and global control of TAP TCK

Scan testing scan frames with embedded commands and differential signaling

Transmitter configured for test signal injection to test AC-coupled interconnect

Tap, test, CSU, scan circuitry with top and bottom contacts

Bypass register separately controlled as internal scan circuit by TAP

Built-in self-test circuit

Blocking the effects of scan chain testing upon a change in scan chain topology

Tap decay test circuitry having capture test strobe enable input

IC die with tap lock, test, scan, and up circuitry

Integrated circuit wafer having plural dies with each die including test circuit receiving expected data and mask data from different pads

TMS/TDI and SIPO controller circuitry with tap and trace interfaces

Blocking the effects of scan chain testing upon a change in scan chain topology

Processing apparatus, ion implantation apparatus and ion implantation method

Circuit for testing integrated circuits

Structural testing of integrated circuits

Boundary scan with coarse and fine delay register clock circuitry

Transporting ordered test data, mode select, ready, precharge packet bits

Serial/parallel control, separate tap, master reset synchronizer for tap domains

IC die test, scan, and capture, shift, and update circuitry

Semiconductor test system and method

Addressable tap with address detect and control. and gating circuitry

Wafer scale testing using a 2 signal JTAG interface

Test clock/test mode slect (TCK/TMS), select, data register (DR) connection circuitry between test access port (TAP) and bypass register

Blocking the effects of scan chain testing upon a change in scan chain topology

At speed tap with dual port router and command circuit

IC die top, bottom signals, tap lock, test, scan circuitry

At-speed test of memory arrays using scan

Semiconductor test system and method

Integrated circuit wafer having integrated circuit die with plural comparators receiving expected data and mask data from different pads

Gated state machine circuitry having three clock 2 enable states

Method and apparatus for improving efficiency of testing integrated circuits

Blocking the effects of scan chain testing upon a change in scan chain topology

First, second TAP address control inputs for TAP TMS input

IC test circuitry and adapter with data transport control register

Semiconductor test system and method

Semiconductor chip, stack chip including the same, and testing method thereof

Addressable tap address, state monitor, decode and TMS gating circuitry

IC tap/scan selecting between TDI/SI and a test pattern source

IC top/bottom surfaces coupled to test, scan, and comparator circuitry

Blocking the effects of scan chain testing upon a change in scan chain topology

Tap linking module test access port controller with enable input

Address and command port with tap and master controller circuitry

First/second die, channel interfaces, TAPs, and TLMs with common clock

IC test circuitry with tri-state buffer, comparator, and scan cell

Integrated circuit with plural comparators receiving expected data and mask data from different pads

Operating state machine from reset to poll in to reset

Scan chain latch design that improves testability of integrated circuits

Tap controller having TMS, TCK, enable inputs and control outputs

Semiconductor test system and method

Scan test port capture/shift signals maintaining/transitioning sequence and idle states

Asynchronous programmable JTAG-based interface to debug any system-on-chip states, power modes, resets, clocks, and complex digital logic

Semiconductor apparatus with boundary scan test circuit

IC with comparator receiving expected and mask data from pads

At speed TAP, dual port router, and command flip-flop circuitry

IC linking module gating inputs of TAP select and enable

Scan circuitry for testing input and output functional paths of an integrated circuit

Circuitry selectively coupling scan circuitry to test data out lead

Blocking the effects of scan chain testing upon a change in scan chain topology

Boundary scan chain for stacked memory

Efficient scan latch systems and methods

2-pin interface with data input, data output, address match input

Interface logic for a multi-core system-on-a-chip (SoC)

Method for JTAG-driven remote scanning

Probeless testing of pad buffers on wafer

IC scan and test circuitry with up control circuitry

Scan test controller with state machine and gates

I/O linking, TAP selection and multiplexer remove select control circuitry

Integrated circuit chip and memory device

Method and apparatus for testing I/O boundary scan chain for SoC's having I/O's powered off by default

Remote boundary scanning

JTAG-based programming and debug

System, method and computer-accessible medium for design for testability support for launch and capture of power reduction in launch-off-capture testing

IC TAP with address, state monitor, and state decode circuitry

Transitioning POLL IN to set MRST and CE high states

Scan, test, and control circuits coupled to IC surfaces contacts

Testing an integrated circuit device with multiple testing protocols

Apparatus for JTAG-driven remote scanning

Maximizing Re-Use of External Pins of an Integrated Circuit for Testing

Boundary scan chain for stacked memory

Control circuit for connector

Methods and apparatus for testing multiple-IC devices

Verifying and detecting boundary scan cells to input/output mapping

METHODS FOR INVOKING TESTING USING REVERSIBLE CONNECTORS

CONNECTORS FOR INVOKING AND SUPPORTING DEVICE TESTING

Packet-based propagation of testing information

Methods and apparatus for testing multiple-IC devices

Circuit test interface and test method thereof

Memory hard macro partition optimization for testing embedded memories

Test access and scan test ports with lockout signal terminal

Programming the behavior of individual chips or strata in a 3D stack of integrated circuits

Programming the behavior of individual chips or strata in a 3D stack of integrated circuits

TESTING STACKED DIE

State machine transitioning states from sequence 3 to idle 2

Address and command port connecting trace circuitry and TAP domain

Method and apparatus for testing a semiconductor device

IC TAP with IR select output and controller enable input

Test access architecture for TSV-based 3D stacked ICS

IC dies with serarate connections to expected and mask data

Tap with address, state monitor and gating circuitry

Efficient wrapper cell design for scan testing of integrated

TAP test clock control circuitry connected to device address port

Parallel scan paths with stimulus and header data circuitry

Integrated circuit comprising scan test circuitry with parallel reordered scan chains

INTEGRATED CIRCUIT FOR TESTING USING A HIGH-SPEED INPUT/OUTPUT INTERFACE

Scan collector and parallel scan paths with controlled output buffer

Pad switch cells selectively coupling test leads to test pads

TDI multiplexer gating controlled by override selection logic

Master reset and synchronizer circuit with data and clock inputs

JTAG apparatus and method for implementing JTAG data transmission

I/O and comparator circuitry with compare gate and mask circuitry