TEMPLATIZED MEMORY PATTERN GENERATOR AND METHOD

TESTER CHANNEL MULTIPLEXING IN TEST EQUIPMENT

Clock recovery unit adjustment

Test system that converts command syntaxes

Apparatus for performing multiple tests on a device under test

Tester channel multiplexing in test equipment

SHORT PATTERN WAVEFORM DATABASE BASED MACHINE LEARNING FOR MEASUREMENT

Memory device test method, apparatus, and system, medium, and electronic device

TEST AND MEASUREMENT SYSTEM

Chip testing circuit and testing method thereof

Trajectory-optimized test pattern generation for built-in self-test

System, apparatus and method for in-field self testing in a diagnostic sleep state

DEVICE INSPECTION METHOD

System, apparatus and method for probeless field scan of a processor

Narrow-parallel scan-based device testing

System, apparatus and method for in-field self testing in a diagnostic sleep state

Oscilloscope and method

Receiving test input message packets and transmitting modulated acknowledgement packets

System, apparatus and method for functional testing of one or more fabrics of a processor

ATE compatible high-efficient functional test

Virtual probe sequencing

Test architecture with a small form factor test board for rapid prototyping

Test architecture with an FPGA based test board to simulate a DUT or end-point

Automatic test equipment (ATE) platform translation

Configuration and testing method and system for FPGA chip using bumping process

De/mod, messaging circuitry coupling first/second function/test circuitry to power pads

Multiple rate signature test to verify integrated circuit identity

Apparatus and method of generating test pattern, test system using the same, and computer program therefor

Test messaging demodulate and modulate on separate power pads

Multi-bank digital stimulus response in a single field programmable gate array

Multiple rate signature test to verify integrated circuit identity

Device including programmable logic element and programmable switch

Device for generating test pattern

Test messaging demodulate and modulate on separate power pads

Parallel scan distributors and collectors and process of testing integrated circuits

Executing code on a test instrument in response to an event

System on chip including built-in self test circuit and built-in self test method thereof

Test pattern generation device, fault detection system, test pattern generation method, program and recording medium

Method and apparatus for device testing using multiple processing paths

Parallel scan paths with three bond pads, distributors and collectors

Test architecture having multiple FPGA based hardware accelerator blocks for testing multiple DUTs independently

Tester with acceleration on memory and acceleration for automatic pattern generation within a FPGA block

Embedded tester

INSPECTION APPARATUS, INSPECTION SYSTEM AND INSPECTION METHOD

Tester hardware

Test messaging and control circuitry coupled to power pad

INTEGRATED CIRCUIT AND TESTING METHOD

Parallel scan paths with three bond pads, distributors and collectors

Semiconductor module, test system and method employing the same

TEST APPARATUS AND TEST METHOD

Adaptive test sequence for testing integrated circuits

Test apparatus

Test data management system and method

General purpose protocol engine

METHOD OF TESTING AN OBJECT AND APPARATUS FOR PERFORMING THE SAME

TEST APPARATUS AND DEBUG METHOD

Measured device and test system utilizing the same

TECHNIQUES FOR ERROR DIAGNOSIS IN VLSI SYSTEMS

Data latch circuit

Test apparatus and test method

Test module and test method

Logic applying serial test bits to scan paths in parallel

Semiconductor integrated circuit device

Test apparatus and information processing system

TEST APPARATUS AND INFORMATION PROCESSING SYSTEM

TEST APPARATUS, INFORMATION PROCESSING SYSTEM AND DATA TRANSFER METHOD

IC with first and second distributors collectors and scan paths

Test apparatus and test method

Logic applying different bit positions to respective scan paths

DEVICE TEST AND DEBUG USING POWER AND GROUND TERMINALS

Test apparatus and test method

TEST PATTERN GENERATION APPARATUS, TEST PATTERN GENERATION METHOD, AND MEDIUM STORING TEST PATTERN GENERATION PROGRAM

General purpose protocol engine

Test equipment

Tester, method for testing a device under test and computer program

Testable integrated circuit and test data generation method

Deterministic component model identifying apparatus, identifying method, program, recording medium, test system and electronic device

Parallel scan distributors and collectors and process of testing integrated circuits

Parallel scan distributors and collectors and process of testing integrated circuits

Parallel scan distributors and collectors and process of testing integrated circuits

Parallel scan distributors and collectors and process of testing integrated circuits

Data processing device and methods thereof

Signal generation and detection apparatus and tester

Semiconductor integrated circuit device

Testing module, testing apparatus and testing method

Testing module, testing apparatus and testing method

Applying test response start and command signals to power lead

Parallel scan distributors and collectors and process of testing integrated circuits

Parallel scan distributors and collectors and process of testing integrated circuits

Parallel scan distributors and collectors and process of testing integrated circuits

Systems and methods for storing test data and accessing test data

Method and apparatus for improving data transfer

Bit pattern synchronization in acquired waveforms

Semiconductor device including test element group and method for testing therefor

IC testing methods and apparatus

Pattern generation for test apparatus and electronic device

Test apparatus and electronic device for generating test signal by using repeated interval in a test instruction stream

Test apparatus and electronic device for generating test signal to a device under test

Instruction address generation for test apparatus and electrical device

Test apparatus for updating a value of the bit position in result register by executing a result register update instruction with predetermined value to generate test pattern

Method and apparatus for cooling non-native instrument in automatic test equipment

Scan distributor loading scan paths simultaneous with loading test data

Tester input/output sharing

Diagnostic Information Capture from Memory Devices with Built-in Self Test

Semiconductor testing device having test result sending back to generate second data

Selecting test circuitry from header signals on power lead

Test apparatus and test method

Apparatus and method for generating test signals after a test mode is completed

Operation monitor system, semiconductor apparatus, and information collection apparatus

Test system of semiconductor device having a handler remote control and method of operating the same

Parallel scan distributors and collectors and process of testing integrated circuits

Input circuit of semiconductor memory device and test system having the same

Test method, test system and assist board

Reduced pattern memory in digital test equipment

Integrated circuit device, diagnosis method and diagnosis circuit for the same

Automatic Test Equipment (ATE) Realized Through Sharing Same Memory Space by Instruction Data and Vector Data

Object-oriented system and method for transforming and loading wafer test data

LSI inspection module, control method for LSI inspection module, communication method between LSI inspection module and inspection apparatus, and LSI inspection method

Test apparatus and test method

Thinning filter and test apparatus

Scoring mechanism for automatically generated test programs

Test apparatus and testing method

Test apparatus, configuration method, and device interface

First and second scan distributors, collectors, controllers, and multiplexers

Scan stream sequencing for testing integrated circuits

Multiple sweep point testing of circuit devices

System and method for linking and loading compiled pattern data

System and method for linking and loading compiled pattern data

Apparatus, system and/or method for converting a serial test to a parallel test

Pattern generator, memory controller, and test device

Pseudo random verification of waveform fault coverage

Measurement control apparatus

Method for testing circuit units to be tested by means of majority decisions and test device for performing the method

Methods and apparatus for optimizing lists of waveforms

Test apparatus with static storage device and test method

Semiconductor testing apparatus

Test method, test receptacle and test arrangement for high-speed semiconductor memory devices

Test device and test module

Apparatus for delay fault testing of integrated circuits