171918 ⎘
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere; Testing of electronic circuits, e.g. by signal tracer; Testing of digital circuits; Functional testing; Tester hardware, i.e. output processing circuits; Stimuli generation or application of test patterns to the device under test [DUT]; Storing and outputting test patterns using compression techniques, e.g. patterns sequencer
Programmable scan chain debug technique
#2Method of testing electronic circuits and corresponding circuit
#3Suspect resolution for scan chain defect diagnosis
#4Method of testing electronic circuits and corresponding circuit
#5Smart and efficient protocol logic analyzer configured within automated test equipment (ATE) hardware
#6Frequent pattern mining method and apparatus
#7In-field self-test controller for safety critical automotive use cases
#8Semiconductor device and scan test method including writing and reading test data
#9Parallel test device and method
#10Test scheduling and test access in test compression environment
#11Device and method for generating input control signals of a serialized compressed scan circuit
#12Parallel test device and method
#13Localizing fault flop in circuit by using modified test pattern
#14Continuous application and decompression of test patterns and selective compaction of test responses
#15TEST APPARATUS, TEST MODULE AND TEST METHOD
#16TEST MODULE, TEST APPARATUS AND TEST METHOD
#17Low power decompression of test cubes
#18Compressing test responses using a compactor
#19Compression based on deterministic vector clustering of incompatible test cubes
#20Chip testing circuit
#21Chip and system utilizing the same
#22Fault diagnosis of compressed test responses
#23Method for generating, from a test cube set, a generator configured to generate a test pattern
#24Method and apparatus for testing logic circuit designs
#25COMPRESSION AND DECOMPRESSION OF STIMULUS AND RESPONSE WAVEFORMS IN AUTOMATED TEST SYSTEMS
#26Systems and Methods for Scan Chain Testing Using Analog Signals
#27System and method for adaptive nonlinear test vector compression
#28Compressing test responses using a compactor
#29Compression and decompression of stimulus and response waveforms in automated test systems
#30Low power decompression of test cubes
#31Integrated circuit device, diagnosis method and diagnosis circuit for the same
#32Method and apparatus for testing logic circuit designs
#33Compressed logic sample storage
#34Integrated circuit tester with software-scaleable channels
#35Methods and apparatus for data compression
#36Integrated circuit test system
#37Test apparatus and method for testing a circuit unit
#38Thinning filter and test apparatus
#39Parallel compression test circuit of memory device
#40Scoring mechanism for automatically generated test programs
#41Methods and apparatus for programming and operating automated test equipment
#42Methods and apparatus for providing scan patterns to an electronic device
#43Fault diagnosis of compressed test responses having one or more unknown states
#44Adaptive fault diagnosis of compressed test responses
#45Fault diagnosis of compressed test responses
#46Externally-loaded weighted random test pattern compression
#47Scan stream sequencing for testing integrated circuits
#48Systems and methods for processing automatically generated test patterns
#49Method of efficiently compressing and decompressing test data using input reduction
#50Implementation of test patterns in automated test equipment
#51Tester channel count reduction using observe logic and pattern generator
#52Methods and apparatus for optimizing lists of waveforms
#53Cost estimation for device testing
#54Apparatus and method for testing circuit units to be tested
#55Method and system for construction of a highly efficient and predictable sequential test decompression logic
#56Method and system for improving efficiency of sequential test compression using overscan
#57Method and system for improving efficiency of XOR-based test compression using an embedded serializer-deserializer