190279 ⎘
Accessing, addressing or allocating within memory systems or architectures; Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems; Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
Method and apparatus to process SHA-2 secure hashing algorithm
#902Memory mapping for object-based storage devices
#903Memory mapping for object-based storage devices
#904Circuit modification
#905Enabling poll/select style interfaces with coherent accelerators
#906Memory management method and device and memory controller
#907Efficient translation reloads for page faults with host accelerator directly accessing process address space without setting up DMA with driver and kernel by process inheriting hardware context from the host accelerator
#908Efficient translation reloads for page faults with host accelerator directly accessing process address space without setting up DMA with driver and kernel by process inheriting hardware context from the host accelerator
#909Reducing page invalidation broadcasts in virtual storage management
#910Reducing page invalidation broadcasts in virtual storage management
#911Reducing latency by persisting data relationships in relation to corresponding data in persistent memory
#912Address re-ordering mechanism for efficient pre-fetch training in an out-of order processor
#913Memory management using virtual address masking
#914Multi-core shared page miss handler
#915Method to share a coherent accelerator context inside the kernel
#916Method to share a coherent accelerator context inside the kernel
#917Apparatus and method for accelerating operations in a processor which uses shared virtual memory
#918Method and apparatus to process SHA-2 secure hashing algorithm
#919Multi-stage translation of prefetch requests
#920System and method for retaining DRAM data when reprogramming reconfigurable devices with DRAM memory controllers incorporating a data maintenance block colocated with a memory module or subsystem
#921Technologies for execute only transactional memory
#922Hardware mechanism for performing atomic actions on remote processors
#923Data processor
#924Systems and methods storing a page fault virtual address to prevent unnecessary page table walks
#925HAZARD CHECKING
#926Asynchronously clearing page frames
#927Mapping graphics resources to linear arrays using a paging system
#928METHOD AND APPARATUS FOR PREVENTING UNAUTHORIZED ACCESS TO CONTENTS OF A REGISTER UNDER CERTAIN CONDITIONS WHEN PERFORMING A HARDWARE TABLE WALK (HWTW)
#929Supporting data compression using match scoring
#930Memory management for a hierarchical memory system
#931Memory management and device
#932Memory corruption prevention system
#933Information processing device including host device and semiconductor memory device having a block rearrangement to secure free blocks
#934Efficiently generating selection masks for row selections within indexed address spaces
#935Secure processor and a program for a secure processor
#936Secure processor and a program for a secure processor
#937Backward compatibility by restriction of hardware resources
#938Latency reduction for direct memory access operations involving address translation
#939Transactional memory operations with write-only atomicity
#940Systems and methods for accessing a unified translation lookaside buffer
#941Translation lookaside buffer that employs spacial locality
#942Address range priority mechanism
#943Transactional memory operations with read-only atomicity
#944Translation buffer unit management
#945System and methods for executing encrypted code
#946MULTI-PAGE CHECK HINTS FOR SELECTIVE CHECKING OF PROTECTED CONTAINER PAGE VERSUS REGULAR PAGE TYPE INDICATIONS FOR PAGES OF CONVERTIBLE MEMORY
#94764KB page system that supports 4KB page operations
#948Access log and address translation log for a processor
#949Page compression strategy for improved page out process
#950Dynamic page table edit control
#951Generating data tables
#952Hot page selection in multi-level memory hierarchies
#953Instruction and logic for characterization of data access
#954Accelerated address indirection table lookup for wear-leveled non-volatile memory
#955Mapping processing method for a cache address in a processor to provide a color bit in a huge page technology
#956MEMORY MANAGEMENT UNIT AND OPERATING METHOD THEREOF
#957Instructions and logic to provide advanced paging capabilities for secure enclave page caches
#958Reserving a storage area and building page frame table entries
#959Supporting secure memory intent
#960Reserving a storage area and building page frame table entries
#961Cache memory system and processor system
#962Processor including single invalidate page instruction
#963Translation lookaside buffer
#964Real-time cache behavior forecast using hypothetical cache
#965Cache coherence in multi-compute-engine systems
#966Translation lookaside buffer in memory
#967Apparatus and method for accelerating operations in a processor which uses shared virtual memory
#968Tracking the content of a cache using a way tracker having entries with a cache miss indicator
#969PROGRAM EXECUTION DEVICE AND COMPILER SYSTEM
#970Method, apparatus, and storage medium for writing data into persistent storage device
#971Suppressing virtual address translation utilizing bits and instruction tagging
#972Apparatus having main TLB and local TLBS, and configured to set selected size for new entry allocated to local TLB to a default size
#973Object memory management unit
#974Photonics-Optimized Processor System
#975Managing memory based on hint data generated from mapping data entries
#976Object memory management unit
#977Computer processor with address register file
#978Burst translation look-aside buffer
#979Physical address management in solid state memory
#980Maintaining command order of address translation cache misses and subsequent hits
#981Virtual Machines Backed by Host Virtual Memory
#982Selective purging of PCI I/O address translation buffer
#983Instruction and logic for support of code modification in translation lookaside buffers
#984Virtual register file
#985Pooled memory address translation
#986Memory system and operating method thereof
#987Command-driven translation pre-fetch for memory management units
#988Error detection using a logical address key
#989Algorithm and apparatus to deploy virtual machine monitor on demand
#990Apparatuses and methods to prevent execution of a modified instruction
#991Memory system
#992Method to efficiently implement synchronization using software managed address translation
#993Dynamic address translation with fetch protection in an emulated environment
#994Storage device, a host system including the storage device, and a map table updating method of the host system
#995Managing reuse information with multiple translation stages
#996MANAGING REUSE INFORMATION FOR MEMORY PAGES
#997Memory management for address translation including detecting and handling a translation error condition
#998CACHE SYSTEM WITH A PRIMARY CACHE AND AN OVERFLOW FIFO CACHE
#999Memory access and detecting memory failures using dynamically replicated memory based on a replication policy
#1000Selective translation lookaside buffer search and page fault
#1001Dynamic guest virtual machine identifier allocation
#1002Apparatus and method for transactional memory and lock elision including an abort instruction to abort speculative execution
#1003Adaptive mode translation lookaside buffer search and access fault
#1004Method and apparatus for accessing data stored in a storage system that includes both a final level of cache and a main memory
#1005Address translation in a data processing apparatus
#1006Method and apparatus for accessing hardware resource
#1007HARDWARE-SUPPORTED PER-PROCESS METADATA TAGS
#1008Method, apparatus, and system for speculative abort control mechanisms
#1009Memory signal buffers and modules supporting variable access granularity
#1010Updatable address lookup application program interface
#1011Storing a system-absolute address (SAA) in a first level translation look-aside buffer (TLB)
#1012Address translation cache that supports simultaneous invalidation of common context entries
#1013Hiding page translation miss latency in program memory controller by next page prefetch on crossing page boundary
#1014Memory system for reliable predicted sequential read operation
#1015Simultaneous invalidation of all address translation cache entries associated with an X86 process context identifier
#1016Identification of page sharing opportunities within large pages
#1017Method and apparatus for querying physical memory address
#1018Cache system with a primary cache and an overflow cache that use different indexing schemes
#1019Dynamic pinning of virtual pages shared between different type processors of a heterogeneous computing platform
#1020Multilevel cache-based data read/write method and apparatus, and computer system
#1021Managing buffered communication between cores
#1022Managing buffered communication between sockets
#1023Method and system for compressing data for a translation look aside buffer (TLB)
#1024Wireless memory interface
#1025Caching TLB translations using a unified page table walker cache
#1026Translation lookaside buffer management
#1027Filtering translation lookaside buffer invalidations
#1028System supporting multiple partitions with differing translation formats
#1029Apparatus and method for transactional memory and lock elision including abort and end instructions to abort or commit speculative execution
#1030Method and Device for Storing Direct Table
#1031Memory system and non-transitory computer readable recording medium
#1032Coalescing adjacent gather/scatter operations
#1033System supporting multiple partitions with differing translation formats
#1034Coalescing adjacent gather/scatter operations
#1035Coalescing adjacent gather/scatter operations
#1036Coalescing adjacent gather/scatter operations
#1037Coalescing adjacent gather/scatter operations
#1038Coalescing adjacent gather/scatter operations
#1039Coalescing adjacent gather/scatter operations
#1040TLB Management Method and Computer
#1041Coalescing adjacent gather/scatter operations
#1042Logical-to-physical block mapping inside the disk controller: accessing data objects without operating system intervention
#1043Method and apparatus for determining physical address
#1044Hardware-assisted memory compression management using page filter and system MMU
#1045Methods and systems for memory de-duplication
#1046Information processing device including host device and semiconductor memory device having a plurality of address conversion information
#1047Method and apparatus for monitoring system performance and dynamically updating memory sub-system settings using software to optimize performance and power consumption
#1048Method and Apparatus For Deterministic Translation Lookaside Buffer (TLB) Miss Handling
#1049Method and apparatus for improved thread selection
#1050Synchronizing a translation lookaside buffer with page tables
#1051Instruction and logic for support of code modification in translation lookaside buffers
#1052Descriptor ring management
#1053Immediate branch recode that handles aliasing
#1054Efficient error handling mechanisms in data storage systems
#1055Address translation services for direct accessing of local memory over a network fabric
#1056Paging of external memory
#1057Methods for scheduling read commands and apparatuses using the same
#1058Systems and methods for accessing memory
#1059Method and apparatus for accessing data stored in a storage system that includes both a final level of cache and a main memory
#1060System and method for performing message driven prefetching at the network interface
#1061Systems and methods for exposing a result of a current processor instruction upon exiting a virtual machine
#1062Virtualization of memory for programmable logic
#1063Multiprocessor computer system
#1064Efficient address translation caching in a processor that supports a large number of different address spaces
#1065LINEAR TO PHYSICAL ADDRESS TRANSLATION WITH SUPPORT FOR PAGE ATTRIBUTES
#1066Synchronizing a translation lookaside buffer with an extended paging table
#1067Synchronizing a translation lookaside buffer with an extended paging table
#1068Synchronizing a translation lookaside buffer with an extended paging table
#1069Synchronizing a translation lookaside buffer with an extended paging table
#1070Synchronizing a translation lookaside buffer with an extended paging table
#1071Synchronizing a translation lookaside buffer with an extended paging table
#1072Multi-petascale highly efficient parallel supercomputer
#1073Maintaining processor resources during architectural events
#1074Detecting cache conflicts by utilizing logical address comparisons in a transactional memory
#1075Apparatus and method for allocating virtual memory addresses to continuous physical addresses
#1076Detecting cache conflicts by utilizing logical address comparisons in a transactional memory
#1077Transactional memory operations with write-only atomicity
#1078Transactional memory operations with read-only atomicity
#1079Transactional memory operations with write-only atomicity
#1080Transactional memory operations with read-only atomicity
#1081Memory switching protocol when switching optically-connected memory
#1082MEMORY ADDRESS TRANSLATION
#1083Identification of low-activity large memory pages
#1084Identification of low-activity large memory pages
#1085Handling memory access protection and address translation in a data processing apparatus
#1086Translation lookaside buffer
#1087Enabling virtualization of a processor resource
#1088Facilitating efficient prefetching for scatter/gather operations
#1089CAM cell for overwriting comparison data during mask operation
#1090Intelligent GPU memory pre-fetching and GPU translation lookaside buffer management
#1091Selective prefetching of physically sequential cache line to cache line that includes loaded page table entry
#1092Persistent memory for processor main memory
#1093Systems and methods for accessing a unified translation lookaside buffer
#1094Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer
#1095Multiplexed memory for segments and pages
#1096Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spaces
#1097Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer
#1098Using broadcast-based TLB sharing to reduce address-translation latency in a shared-memory system with optical interconnect
#1099Storage unit controller and control method thereof, and storage device
#1100Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spaces
#1101Binary translation reuse in a system with address space layout randomization
#1102Address translation structures to provide separate translations for instruction fetches and data accesses
#1103Hierarchical translation structures providing separate translations for instruction fetches and data accesses
#1104Address translation structures to provide separate translations for instruction fetches and data accesses
#1105Hierarchical translation structures providing separate translations for instruction fetches and data accesses
#1106Selective purging of PCI I/O address translation buffer
#1107Selective purging of PCI I/O address translation buffer
#1108OPERATING SYSTEM/HYPERVISOR EFFICIENCIES FOR SUB-DIVIDED PRIVILEGE LEVELS
#1109Guest-programmable location of advanced configuration and power interface (ACPI) tables in virtualized systems
#1110Invalidating stored address translations
#1111Method and apparatus for accessing data stored in a storage system that includes both a final level of cache and a main memory
#1112Memory system
#1113Information processing apparatus and method
#1114Power efficient level one data cache access with pre-validated tags
#1115Using virtual disk in virtual machine live migration
#1116Synchronizing a translation lookaside buffer with an extended paging table
#1117Synchronizing a translation lookaside buffer with an extended paging table
#1118Method and system for implementing multi-stage translation of virtual addresses
#1119Memory mapping method of nonvolatile memory system and system for providing the memory mapping method
#1120Look-aside processor unit with internal and external access for multicore processors
#1121Systems and methods for memory management in a dynamic translation computer system
#1122System, apparatus, and method for transparent page level instruction translation
#1123Providing memory system programming interfacing
#1124Increasing granularity of dirty bit information
#1125Address translation in a data processing apparatus
#1126Device for selecting a level for at least one read voltage
#1127Load-through fault mechanism
#1128SYSTEM AND METHOD FOR PROVIDING CLIENT-SIDE ADDRESS TRANSLATION IN A MEMORY MANAGEMENT SYSTEM
#1129MEMORY ALLOCATION AND PAGE ADDRESS TRANSLATION SYSTEM AND METHOD
#1130Management method of virtual-to-physical address translation system using part of bits of virtual address as index
#1131I/O controller and method for operating an I/O controller
#1132Mechanisms to accelerate transactions using buffered stores
#1133Physical address management in solid state memory
#1134Efficient error handling mechanisms in data storage systems
#1135INFORMATION PROCESSING APPARATUS AND DATA TRANSFER CONTROL METHOD
#1136Method and apparatus for performing a bus lock and translation lookaside buffer invalidation
#1137Final level cache system and corresponding methods
#1138Maintaining processor resources during architectural events
#1139Maintaining processor resources during architectural events
#1140Computer processor employing bypass network using result tags for routing result operands
#1141Computer processor with deferred operations
#1142Computer processor employing hardware-based pointer processing
#1143METHOD AND A DEVICE FOR CONTROLLING MEMORY-USAGE OF A FUNCTIONAL COMPONENT
#1144Computer processor employing cache memory with per-byte valid bits
#1145Computer processor employing dedicated hardware mechanism controlling the initialization and invalidation of cache lines
#1146Computer processor employing cache memory storing backless cache lines
#1147Multi-core heterogeneous system translation lookaside buffer coherency
#1148Dynamically determining a translation lookaside buffer flush promotion threshold value
#1149Managing memory regions to support sparse mappings
#1150Method and processor for reducing code and latency of TLB maintenance operations in a configurable processor
#1151Multi-stage address translation for a computing device
#1152Creating a program product or system for executing a perform frame management instruction
#1153Method and apparatus for page-level monitoring
#1154Electronic circuit for fitting a virtual address range to a physical memory containing faulty address
#1155Managing Mirror Copies without Blocking Application I/O
#1156Collapsed address translation with multiple page sizes
#1157Management Of A Memory
#1158Secure memory repartitioning
#1159Translation bypass in multi-stage address translation
#1160Memory management unit
#1161Maintenance of cache and tags in a translation lookaside buffer
#1162Managing Mirror Copies without Blocking Application I/O
#1163Computer system, memory management method and program thereof
#1164Merged TLB structure for multiple sequential address translations
#1165System-on-chip and address translation method thereof using a translation lookaside buffer and a prefetch buffer
#1166Pre-fetch in a multi-stage memory management system
#1167I/O memory management unit providing self invalidated mapping
#1168Inter-core cooperative TLB prefetchers
#1169Enhanced pre-fetch in a memory management system
#1170MEMORY CONTROL DEVICE, HOST COMPUTER, INFORMATION PROCESSING SYSTEM AND METHOD OF CONTROLLING MEMORY CONTROL DEVICE
#1171Semiconductor storage device and semiconductor storage device control method
#1172Storage system and writing method thereof
#1173Synchronizing a translation lookaside buffer with an extended paging table
#1174Virtualization system using hardware assistance for page table coherence
#1175Cache pre-fetch merge in pending request buffer
#1176Identification of page sharing opportunities within large pages
#1177Shared virtual memory between a host and discrete graphics device in a computing system
#1178Managing a translation lookaside buffer
#1179System method for memory virtualization control logic for translating virtual memory in space of guest memory based on translated codes in response to memory failure
#1180Computing apparatus, computing method, and computing program
#1181Memory system
#1182Mechanism for issuing requests to an accelerator from multiple threads
#1183GPU accelerated address translation for graphics virtualization
#1184Linear to physical address translation with support for page attributes
#1185Linear to physical address translation with support for page attributes
#1186Providing metadata in a translation lookaside buffer (TLB)
#1187System and method for reading and writing data with a shared memory hash table
#1188Implementing computational memory from content-addressable memory
#1189Enabling virtualization of a processor resource
#1190Logical address translation
#1191Global maintenance command protocol in a cache coherent system
#1192Method and apparatus for preventing non-temporal entries from polluting small structures using a transient buffer
#1193MEMORY MANAGEMENT APPARATUS AND MEMORY MANAGEMENT METHOD THEREOF
#1194Linear to physical address translation with support for page attributes
#1195Memory address translation
#1196Instructions and logic to provide advanced paging capabilities for secure enclave page caches
#1197Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
#1198ADDRESS TRANSLATION IN A SYSTEM USING MEMORY STRIPING
#1199Frame buffer access tracking via a sliding window in a unified virtual memory system
#1200Multi-threaded memory management