Semiconductor device and method for controlling plural chips

Dual slc/qlc programming and resource releasing

Processor system and method for increasing data-transfer bandwidth during execution of a scheduled parallel process

Narrow DRAM channel systems and methods

Method and system for logical to physical (L2P) mapping for data-storage device comprising nonvolatile memory

Method and system for performing read/write operation within a computing system hosting non-volatile memory

Scalable input/output system and techniques to transmit data between domains without a central processor

High-performance, high-capacity memory systems and modules

CONFIGURABLE MEMORY BLOCKS FOR LIDAR MEASUREMENTS

Data redirection upon failure of a program operation

Apparatus and method for data transmission and readable storage medium

Packet routing between memory devices and related apparatuses, methods, and memory systems

Data storage apparatus and method, and readable storage medium

Memory system and operating method thereof

Methods and apparatus to facilitate atomic compare and swap in cache for a coherent level 1 data cache system

Memory controller and method of operating the same

ONE-WAY BUS BRIDGE

Device for interfacing between memory device and memory controller, package and system including the device

Cache metadata management

Detection of compromised storage device firmware

Memory interface having multiple snoop processors

High capacity memory system using standard controller component

Memory module with data buffering

Storage device and method of operating the same

Storage system and method for crash analysis

Reconfigurable parallel processing

Computer memory expansion device and method of operation

Host controller interface using multiple circular queue, and operating method thereof

Fault tolerant memory systems and components with interconnected and redundant data interfaces

ZNS parity swapping to DRAM

Memory controller, memory system, and control method of memory system

Execution space agnostic device drivers

Gateway processing

Dynamically sized redundant write buffer with sector-based tracking

Controller command scheduling in a memory system to increase command bus utilization

High-throughput low-latency hybrid memory module

Local non-volatile memory express virtualization device

SYSTEMS, METHODS, AND DEVICES FOR NEAR DATA PROCESSING

Non-interrupting portable page request interface

Victim cache that supports draining write-miss entries

Packet processing system, method and device utilizing a port client chain

Acceleration circuitry for posit operations

STORING TRANSLATION LAYER METADATA IN HOST MEMORY BUFFER

Storage device for interfacing with host and method of operating the host and the storage device

Memory system design using buffer(s) on a mother board

Processing system with interspersed processors DMA-FIFO

Memory module with reduced read/write turnaround overhead

Semiconductor memory devices and memory systems

Memory data security

Processing system comprising a queued serial peripheral interface, related integrated circuit, device and method

Memory controller and method for monitoring accesses to a memory module

High-level synthesis (HLS) method and apparatus to specify parallelism in computer hardware

Method and system for controlling data response with aid of attribute of transaction identifier

Memory systems, modules, and methods for improved capacity

Single command for reading then clearing a memory buffer

Decoder performing iterative decoding, and storage device using the same

Data storage system capable of performing interleaving scatter transmissions or interleaving gather transmissions

Intelligent durability acknowledgment in a storage system

Synchronous memory bus access to storage media

System and method for optimizing DRAM bus switching using LLC

Memory controller and method of operating the same

System and method for performing erasure coding in a distributed storage system

QUALITY OF SERVICE CONTROL FOR READ OPERATIONS IN MEMORY SYSTEMS

Dedicated design for testability paths for memory sub-system controller

Semiconductor memory device and method of controlling the same

Memory system for handling program failure and an operating method thereof

Storage device that uses a host memory buffer and a memory management method including the same

Sequential read optimization in a memory sub-system that programs sequentially

Input/output (I/O) loopback function for I/O signaling testing

Dual SLC/QLC programming and resource releasing

Methods and devices for extending USB 3.0-compliant communication over an extension medium

Data storage apparatus and operating method thereof

Shared buffered memory routing

Flexible hardware for high throughput vector dequantization with dynamic vector length and codebook size

Quality of service levels for a direct memory access engine in a memory sub-system

Memory device for adjusting memory capacity per channel and memory system including the same

Computing system for transmitting completion early between serially connected electronic devices

Application-transparent near-memory processing architecture with memory channel network

Systems, methods, and apparatus to enable data aggregation and adaptation in hardware acceleration subsystems

SYSTEM AND METHOD TO PROVIDE SMM RUNTIME TELEMETRY SUPPORT

STAGING BUFFER ARBITRATION

Storage system and method for secure host controller memory buffer access

Elastic buffer in a memory sub-system for debugging information

Storage device including memory controller

Bimodal PHY for low latency in high speed interconnects

Handling operation collisions in a non-volatile memory

Cache for artificial intelligence processor

STORAGE DEVICE AND METHOD OF OPERATING THE SAME

Drift detection in timing signal forwarded from memory controller to memory device

Apparatus and method for writing data in a memory

Method and apparatus for controlling memory using prefetch information

Semiconductor device

Memory module with timing-controlled data buffering

Memory system and method of controlling nonvolatile memory with a write buffer

ADAPTIVE ADDRESS ARBITRATION OPTIMIZATION ON AN I3C BUS

Semiconductor device and access control method

Semiconductor memory systems with on-die data buffering

Memory device performing self-calibration by identifying location information and memory module including the same

Method and system with improved memory input and output speed

Memory device, memory system including memory device and vehicle-based system including memory system

Programmable device configuration memory system

Memory system, memory controller and method for operating memory controller

Folded memory modules

Data processing method and device for performing a convolution operation

High bandwidth SDRAM controller

Methods and apparatus for fabric interface polling

Method, computer program, electronic memory medium, device for providing a datum

RAID storage-device-assisted read-modify-write system

Protection scheme for sensor segmentation in virtualization application

Memory device with a training buffer and method of operating the same

Systems and methods for efficient data buffering

Peripheral bus video communication using internet protocol

Memory system having a memory controller and a memory device having a page buffer

Sparse matrix multiplication acceleration mechanism

Prefetching of completion notifications and context

Data redirection upon failure of a program operation

MEMORY SYSTEM INCLUDING HETEROGENEOUS MEMORIES, COMPUTER SYSTEM INCLUDING THE MEMORY SYSTEM, AND DATA MANAGEMENT METHOD THEREOF

Apparatus and method for improving input/output throughput of memory system

Memory system and method of controlling nonvolatile memory

Memory interface for a multi-threaded, self-scheduling reconfigurable computing fabric

Using dynamic bursts to support frequency-agile memory interfaces

Multi-deck memory device including buffer circuitry under array

Controlling data transfers between a tier of persistent data storage and processor memory with a high-speed fabric controller

Memory refresh operations using reduced power

Reconfigurable parallel processing with various reconfigurable units to form two or more physical data paths and routing data from one physical data path to a gasket memory to be used in a future physical data path as input

Memory module and registered clock driver with configurable data-rank timing

Computing system for reducing latency between serially connected electronic devices

Methods for Using High-Speed Data Communication Fabric to Enable Cross-System Command Buffer Writing for Data Retrieval in Cloud Gaming

Data processing system with adjustable speed of processor and operating method thereof

Methods for using high-speed data communication fabric to enable cross-system command buffer reading for data retrieval in cloud gaming

Systems implementing high-speed data communication fabric for cloud gaming data storage and retrieval

Methods implementing doorbell register/file identification table with high-speed data communication fabric for cloud gaming data storage and retrieval

Storage device, memory system, and operating method for managing host-resident L2P map cache

Object-oriented memory

Object-oriented memory client

Object-oriented memory for client-to-client communications

System and method to secure embedded controller flashing process

Semiconductor device including a bus arbiter

Methods for using extended physical region page lists to improve performance for solid-state drives and devices thereof

Memory system and method of operating the same

Memory system, data processing system and operation method of the same

Methods and apparatus for scheduling time sensitive operations among independent processors

Memory system and storage device including printed circuit board with subset of channels arranged in point-to-point topology and subset of channels arranged in daisy-chain topology

Reconfigurable parallel processing with a temporary data storage coupled to a plurality of processing elements (PES) to store a PE execution result to be used by a PE during a next PE configuration

Internal management traffic regulation for memory sub-systems

Memory with alternative command interfaces

Multi-mode memory module and memory component

Memory system, memory controller and operating method

Method, apparatus and computer program product for processing I/O request

Apparatus and method and computer program product for handling flash physical-resource sets

Method and computer program product and apparatus for multi-namespace data access

Semiconductor memory devices and memory systems

Memory module threading with staggered data transfers

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING SYSTEM, AND INFORMATION PROCESSING METHOD

Memory access technology and computer system

Memory device and operating method of the memory device

Non-volatile dual inline memory module (NVDIMM) for supporting dram cache mode and operation method of NVDIMM

Hybrid computing module

Circular reconfiguration for reconfigurable parallel processor using a plurality of memory ports coupled to a commonly accessible memory unit

Shared memory access for reconfigurable parallel processor using a plurality of memory ports each comprising an address calculation unit

Execution space agnostic device drivers

Memory device for efficiently determining whether to perform re-training operation and memory system including the same

Integrated circuit I/O integrity and degradation monitoring

Victim cache with write miss merging

Victim cache with dynamic allocation of entries

Aggressive write flush scheme for a victim cache

Methods and apparatus for allocation in a victim cache system

Methods and apparatus to facilitate read-modify-write support in a victim cache

Methods and apparatus to facilitate atomic operations in victim cache

Methods and apparatus for inflight data forwarding and invalidation of pending writes in store queue

Methods and apparatus for eviction in dual datapath victim cache system

Methods and apparatus to reduce read-modify-write cycles for non-aligned writes

Methods and apparatus to facilitate fully pipelined read-modify-write support in level 1 data cache using store queue and data forwarding

Methods and apparatus for read-modify-write support in multi-banked data RAM cache for bank arbitration

Methods and apparatus to facilitate write miss caching in cache system

Write merging on stores with different privilege levels

Methods and apparatus to reduce bank pressure using aggressive write merging

Write merging on stores with different tags

Methods and apparatus to facilitate an atomic operation and/or a histogram operation in cache pipeline

Hybrid victim cache and write miss buffer with fence operation

Methods and apparatus to facilitate read-modify-write support in a coherent victim cache with parallel data paths

Streaming engine with deferred exception reporting

Private memory access for reconfigurable parallel processor using a plurality of memory ports each comprising an address calculation unit

Data processing performance enhancement for neural networks using a virtualized data iterator

High capacity memory system with improved command-address and chip-select signaling mode

High performance interconnect physical layer

Memory buffer management and bypass

Data transition in highly parallel database management system

Multiple master, multi-slave serial peripheral interface

Scatter gather using key-value store

Minimally disruptive data capture for segmented applications

Opportunistic block transmission with time constraints

Non-volatile memory device, method of operating the device, and memory system including the device

System on chip comprising a plurality of master resources

Writing messages in a shared memory architecture for a vehicle

CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME

MEMORY SYSTEM AND METHOD OF OPERATING THE SAME

Memory module with reduced read/write turnaround overhead

Memory system

Bimodal PHY for low latency in high speed interconnects

Handling operation collisions in a non-volatile memory

Memory system design using buffer(s) on a mother board

Memory controller enabling dual-mode access to memory module

Operating method of memory system that checks stored data that is reused and generating a flag/bit signal

Apparatus and method for providing data to a master device

Memory device and cache control method

MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE MEMORY CONTROLLER

Serial connection between management controller and microcontroller

Memory device and computing device using the same

Transaction identification

Memory controller and operating method thereof

Allocation of buffer interfaces for moving data, and related systems, methods and devices

Apparatus and method of optimizing memory transactions to persistent memory using an architectural data mover

Memory system including a plurality of controllers

MEMORY SYSTEM AND OPERATING METHOD THEREOF

Enhancing processing performance of a DNN module by bandwidth control of fabric interface

Bandwidth limiting in solid state drives

System and method for dynamically adjusting a recording bitrate to accommodate a writing speed of a storage device

System and method of FPGA-executed flash translation layer in multiple solid state drives

Scalable input/output system and techniques to transmit data between domains without a central processor

Semiconductor device

Integrated circuit I/O integrity and degradation monitoring

Read/write direction-based memory bank control for imaging

Memory control method, memory control apparatus, and image forming method that uses memory control method

Remote memory management

Handling operation collisions in a non-volatile memory

Storage device for interfacing with host and method of operating the host and the storage device

Memory module with data buffering

Data processing apparatus, network system, packet order control circuit, and data processing method

Hybrid computing module

Memory data security

Controller, memory system including the same, and method of operating the memory system

Memory system for sharing a plurality of memories through a shared channel

Hardware unit for reverse translation in a processor

Methods and devices for extending USB 3.0—compliant communication over an extension medium

Asynchronous communication protocol compatible with synchronous DDR protocol

System and method for routing bus including buffer

Memory system and operation method thereof

Data striping for matching techniques in data compression accelerator of a data processing unit

Storage device and operating method thereof

Storage devices including heterogeneous processors which share memory and methods of operating the same

Input/output (I/O) loopback function for I/O signaling testing

Bandwidth limiting in solid state drives

Data access method and apparatus for accessing shared cache in a memory access manner

Output processor for transaction processing system

Streaming platform architecture for inter-kernel circuit communication for an integrated circuit

Asynchronous update of metadata tracks in response to a cache hit generated via an i/o operation over a bus interface

Storage device that uses a host memory buffer and a memory management method including the same

Method for accessing extended memory, device, and system

Using a machine learning module to select a priority queue from which to process an input/output (I/O) request

Flash memory controller, method and associated electronic device for managing priority of quality detection or garbage collection of block

Memory system

Load reduced nonvolatile memory interface

Read quality of service for non-volatile memory

System and method for supporting data communication in a movable platform

Memory transaction request management for an ordered unit of data items

Beam scanning image processing within an improved graphics processor micro architecture

Memory chip capable of performing artificial intelligence operation and method thereof

High-level synthesis (HLS) method and apparatus to specify pipeline and spatial parallelism in computer hardware

Processing system with interspersed processors with multi-layer interconnect

Storage device and cache area addressing method

Memory systems, modules, and methods for improved capacity

High capacity memory system using standard controller component

Data storage device using a host memory buffer for single-level cell storage and control method for non-volatile memory

Master chip, slave chip, and inter-chip DMA transmission system

Apparatus and method for processing burst read transactions

Drift detection in timing signal forwarded from memory controller to memory device

Integrated circuit that extracts data, neural network processor including the integrated circuit, and neural network device

Instructions for performing multi-line memory accesses

Unified address space for multiple hardware accelerators using dedicated low latency links

Scalable low-latency storage interface

Memory management method and storage controller

Memory management method, memory storage device and memory control circuit unit

DFE open loop training for DDR data buffer and registered clock driver

Systems and methods for hiding operating system kernel data in system management mode memory to thwart user mode side-channel attacks

METHOD AND SYSTEM FOR BUFFER STATE BASED LOW POWER OPERATION IN A MOCA NETWORK

Memory circuit and method thereof

Dropped command truncation for efficient queue utilization in multiprocessor data processing system

Semiconductor memory systems with on-die data buffering

Controller command scheduling in a memory system to increase command bus utilization

Quality of service control for read operations in memory systems

Error correction coding in a dynamic memory module

Multi-core communication acceleration using hardware queue device

Method, system, and apparatus for reducing processor latency

Practical ORAM delegation for untrusted memory on cloud servers

Writing same data on a storage system

High-throughput low-latency hybrid memory module

Gateway processing

Memory package including buffer, expansion memory module, and multi-module memory system

Folded memory modules

Data storage device managing write tag, writing operation method thereof, and storage system including the same

Methods and apparatus for streaming media conversion with reduced buffering memories

Reducing multi-stream data write collision in solid-state data storage devices

System, apparatus and method for providing a local clock signal for a memory array

Core-to-core communication

Data through gateway

Memory with alternative command interfaces

Arbitrated management of a shared non-volatile memory resource

Reconfigurable parallel processing

Memory module