MEMORY SYSTEM AND OPERATING METHOD THEREOF

Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interface

Method for sending by an upstream device to a downstream device data from a virtual channel sharing a same input buffer memory of the downstream device, corresponding computer program and system

System, apparatus and method for simultaneous read and precharge of a memory

Selecting a priority queue from which to process an input/output (I/O) request by training a machine learning module

Selecting a priority queue from which to process an input/output (I/O) request using a machine learning module

Nonvolatile memory module and operation method thereof

Buffered freepointer management memory system

Systems and devices for accessing a state machine

Memory module, memory device, and processing device having a processor mode, and memory system

IMPLIED DIRECTORY STATE UPDATES

Writing block for a receiver

Memory module with timing-controlled data buffering

Memory buffer management and bypass

Memory buffer management and bypass

Data storage device intergrating host read commands and method of operating the same

DYNAMICALLY SHAPING AND SEGMENTING WORK UNITS FOR PROCESSING IN NEURAL NETWORK PROCESSOR

Systems and methods for task switching in neural network processor

Methods and apparatus for transmitting time sensitive data over a tunneled bus interface

Processor and information processing apparatus

System and method for port-to-port communications using direct memory access

Method and Apparatus for Restoring Data after Power Failure for An Open-Channel Solid State Drive

Storage device buffer in system memory space

Memory module threading with staggered data transfers

Bimodal phy for low latency in high speed interconnects

Adaptive interleaving of data transfer requests

Memory controller and method of operating the same

PREFETCH MODULE FOR HIGH THROUGHPUT MEMORY TRANSFERS

Fault tolerant memory systems and components with interconnected and redundant data interfaces

Memory interface and memory system including plurality of delay adjustment circuits shared by memory read and write circuits for adjusting the timing of read and write data signals

METHOD FOR PROCESSING CLIENT REQUESTS IN A CLUSTER SYSTEM, A METHOD AND AN APPARATUS FOR PROCESSING I/O ACCORDING TO THE CLIENT REQUESTS

Semiconductor device

System, apparatus and method for memory mirroring in a buffered memory architecture

Graphics processing microprocessor system having master and slave devices

Memory buffer chip, memory system and method of controlling the memory buffer chip

Memory system and operating method thereof

Storage device including random access memory devices and nonvolatile memory devices

Memory module with reduced read/write turnaround overhead

High capacity memory system with improved command-address and chip-select signaling mode

Scalable, parameterizable, and script-generatable buffer manager architecture

Memory interface having multiple snoop processors

TRANSACTION HANDLING

Performance evaluation apparatus and performance evaluation method

Memory system design using buffer(S) on a mother board

Memory device for adjusting memory capacity per channel and memory system including the same

Offloaded data migration between storage devices

Synchronous memory bus access to storage media

Data receiving apparatus, data transmission and reception system, and control method of data transmission and reception system

Writing same data on a storage system

Securing stream buffers

Packet processing system, method and device utilizing a port client chain

Memory system having a memory controller and a memory device having a page buffer

Memory controller and method of operating the same

Register access in a distributed memory buffer system

Network device and method of operation

Buffering and compressing data sets

Semiconductor memory device and method of controlling the same

Module based data transfer

Techniques to access or operate a dual in-line memory module via multiple data channels

Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interface

Apparatus, methods, and systems for multicast in a configurable spatial accelerator

Supporting timely and context triggered prefetching in microprocessors

Scaling interface architecture between memory and programmable logic

Semiconductor device and bus generator

Relative data width indication for read responses routed by an interconnect

Method, Apparatus, and System for Accessing Memory Device

Method, system, and apparatus for reducing processor latency

Memory access technology and computer system

Electronic device and method for fabricating the same

Memory device and method for operating the same

Method and device for improved advanced microcontroller bus architecture (AMBA) and advanced extensible interface (AXI) operations

Apparatus and method for protecting program memory for processing cores in a multi-core integrated circuit

Neural processing accelerator

Secure digital (SD) to NVMe buffer manager

Frameless telecommunications enclosure

High speed memory interface

Set buffer state instruction

Asynchronous buffer with pointer offsets

Power saving techniques for memory systems by consolidating data in data lanes of a memory bus

Extended selection and alignment of video segments for adaptive streaming

DRAM and method of operating the same in an hierarchical memory system

Apparatuses and methods for providing data to a configurable storage area

METHOD OF OPERATING STORAGE DEVICE CAPABLE OF REDUCING WRITE LATENCY

Method and device for live migration of virtual machine in a multi-root I/O virtualization environment and computing host thereof

Sorting using pipelined compare units

Hierarchical sort/merge structure using a request pipe

Buffer size optimization in a hierarchical structure

Expandable buffer for memory transactions

Data transmission apparatus and data transmission method

Apparatuses and methods for transferring data from memory on a data path

Deallocation of memory buffer in multiprocessor systems

Dual in-line memory module with dedicated read and write ports

Live partition mobility enabled hardware accelerator address translation fault resolution

Processing system with interspersed processors with multi-layer interconnection

Control method for storing data according to buffer pointer at clock signal conversions

System and method for early data pipeline lookup in large cache design

Enabling live migration of virtual machines with passthrough PCI devices

Scalable network-on-chip for high-bandwidth memory

Sensor bus communication system

Using transfer buffer to handle host read collisions in SSD

Electronic device and method for fabricating the same

Reflective memory bridge for external computing nodes

Autonomous prefetch engine

Decoder performing iterative decoding, and storage device using the same

Data storage device and method of operating the same

Cache self-clean engine

Hardware resource expansion system capable of assigning hardware addresses automatically

System, apparatus and method for hardware-based bi-directional communication via reliable high performance half-duplex link

Bit manipulation capable direct memory access

Cache coherency between a device and a processor

Temporarily storing memory contents

Uniform performance monitor for a data storage device and method of operation

Method of using a chip identification device

Method and apparatus for controlling a memory system to perform a safe shutdown of a volatile memory of a host

Solid state drive with reset circuit and reset method thereof

Network server systems, architectures, components and related methods

Bridge device with DMA data transferring to upstream device with reset and clear feature command

Method and apparatus for in-band priority adjustment forwarding in a communication fabric

Shared buffered memory routing

Reading from a mode register having different read and write timing

Methods and devices for extending USB 3.0-compliant communication over an extension medium

Adaptive buffering of data received from a sensor

MEMORY CONTROLLER, MEMORY SYSTEM, INFORMATION PROCESSING SYSTEM, MEMORY CONTROL METHOD, AND PROGRAM

Serial connection between management controller and microcontroller

Techniques for reducing accelerator-memory access costs in platforms with multiple memory channels

Controlling method, channel operating circuit and memory system for executing memory dies with single channel

Memory chip with reduced power consumption, buffer chip module controlling the same and memory module including the same

Active extensible memory hub

FULL-DUPLEX MEMORY ACCESS SYSTEMS AND METHODS FOR IMPROVED QUALITY OF SERVICE (QOS)

Semiconductor integrated circuit device and method for comparing data

Multilevel memory bus system

Using dynamic bursts to support frequency-agile memory interfaces

MEMORY CONTROLLER, MEMORY SYSTEM HAVING THE SAME, AND OPERATING METHOD THEREOF

Buffer device supporting training operations for a plurality of memory devices, and memory module and memory system each including the buffer device

Bidirectional signal conditioning chip including processor determining data transmission direction and type of transmitted data of USB type-C cable and USB type-C cable including the same

Dynamic adaptation of direct memory transfer in a data processing system with mismatched data-bus widths

BUFFERING TRANSACTION REQUESTS TO A SUBSYSTEM VIA A BUS INTERCONNECT

Asynchronous update of metadata tracks in response to a cache hit generated via an I/O operation over a bus interface

Scalable input/output system and techniques to transmit data between domains without a central processor

Computer system and data control method utilizing NVMe and storing commands including an offset address corresponding to a server in a queue

MESSAGE ROUTING IN A MAIN MEMORY ARRANGEMENT

MESSAGE ROUTING IN A MAIN MEMORY ARRANGEMENT

BURST-SIZED LINKED LIST ELEMENTS FOR A QUEUE

Obtaining data in a nonvolatile memory device through the use of descriptors

CACHE BUFFER

Data storing method, memory control circuit unit and memory storage device

Clock tree structure in a memory system

Data storage device and method of operating the same

Format agnostic data transfer method

Data transfer device, image processing device, and imaging device

Semiconductor device including bus controller

Video device and method for embedded data capture on a virtual channel

Electronic device and method for coherent enable/disable on a virtual data channel

Enhancing virtual machine performance using autonomics

Enhancing virtual machine performance using autonomics

System and method for managing data in a ring buffer

DATA STORAGE CONTROLLER

Technologies for increasing reporting granularity of media rendering data transfers

Methods and apparatus for transmitting time sensitive data over a tunneled bus interface

Delayed link compression scheme

Method, apparatus and system for device transparent grouping of devices on a bus

Methods and apparatus for scheduling time sensitive operations among independent processors

Scalable memory-optimized hardware for matrix-solve

System and method for using host command data buffers as extended memory device volatile memory

High-throughput low-latency hybrid memory module

System, apparatus and method for handshaking protocol for low power state transitions

MULTIPLE DEVICE PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) CARD

Storage device for interfacing with host and method of operating the host and the storage device

Method for dynamic arbitration of real-time streams in the multi-client systems

Peripheral interface circuit for serial memory

Buffer controller, memory device, and integrated circuit device

System and method for programming data transfer within a microcontroller

Multi-level data block error detection code

Interconnect systems and methods using memory links to send packetized data between different data handling devices of different memory domains

Chipset with near-data processing engine

Semiconductor device and access control method

BUFFER CIRCUIT AND DEVICE INCLUDING THE SAME

Chipset with near-data processing engine

Cyclic buffer pointer fixing

Dual first and second pointer for memory mapped interface communication with lower indicating process

Memory system, memory controller for memory system, operation method of memory controller, and operation method of user device including memory device

Persistent host memory buffer

Preinstall of partial store cache lines

System and method for dynamic buffer sizing in a computing device

Streaming engine with deferred exception reporting

Peripheral bus video communication using internet protocol

Memory controller and control method thereof

Storage device and method of operating the storage device

Re-ordering buffer for a digital multi-processor system with configurable, scalable, distributed job manager

APPLICATION PROCESSOR INCLUDING COMMAND CONTROLLER AND INTEGRATED CIRCUIT INCLUDING THE SAME

Processing large requests in data storage systems with limited/constant buffer sizes

Memory system with priority processing and operating method thereof

High-level synthesis (HLS) method and apparatus to specify pipeline and spatial parallelism in computer hardware

Multi-channel DIMMs

Adaptive scheduling of memory requests

Bus communication enhancement based on identification capture during bus arbitration

Buffer stage device that can be connected to a serial peripheral interface bus

METHOD FOR PROCESSING CLIENT REQUESTS IN A CLUSTER SYSTEM, A METHOD AND AN APPARATUS FOR PROCESSING I/O ACCORDING TO THE CLIENT REQUESTS

Method and system for fast ordered writes with target collaboration

Live partition mobility enabled hardware accelerator address translation fault resolution

Live partition mobility enabled hardware accelerator address translation fault resolution

Hardware accelerator address translation fault resolution

Hardware accelerator address translation fault resolution

Computing systems relating to serial and parallel interfacing operations

Event-driven schemes for determining suspend/resume periods

Queue management for direct memory access

Data processing performance enhancement for neural networks using a virtualized data iterator

Enhancing processing performance of artificial intelligence/machine hardware by data sharing and distribution as well as reuse of data in neuron buffer/line buffer

Dynamically partitioning workload in a deep neural network module to reduce power consumption

Power-efficient deep neural network module configured for parallel kernel and parallel input processing

Power-efficient deep neural network module configured for executing a layer descriptor list

Processing discontiguous memory as contiguous memory to improve performance of a neural network environment

Minimizing memory reads and increasing performance by leveraging aligned blob data in a processing unit of a neural network environment

Neural network processor using compression and decompression of activation data to reduce memory bandwidth utilization

Reducing power consumption in a neural network processor by skipping processing operations

Power-efficient deep neural network module configured for layer and operation fencing and dependency management

Flexible hardware for high throughput vector dequantization with dynamic vector length and codebook size

Dynamic sequencing of data partitions for optimizing memory utilization and performance of neural networks

USB link bridge

Memory module with data buffering

Scalable low-latency storage interface

Enhancing processing performance of a DNN module by bandwidth control of fabric interface

System, apparatus and method for providing a local clock signal for a memory array

Semiconductor device

Beam scanning image processing within an improved graphics processor microarchitecture

Data storage device

MEMORY MANAGER FOR AUTONOMOUS MEMORY DEVICE

Virtual channel and resource assignment

Controller reading data stored in a memory device using buffers, operating method thereof and memory system including controller

Transaction identification

Scoreboard approach to managing idle page close timeout duration in memory

Transaction handling

Transitioning a buffer to be accessed exclusively by a driver layer for writing immediate data stream

MEMORY SYSTEM AND OPERATING METHOD THEREOF

Direct Network Access by a Memory Mapped Peripheral Device for Scheduled Data Transfer on the Network

Recording apparatus, control method, and storage medium

Dynamic memory remapping to reduce row-buffer conflicts

Shared memory access for a reconfigurable parallel processor with a plurality of chained memory ports

Private memory access for a reconfigurable parallel processor using a plurality of chained memory ports

Circular reconfiguration for a reconfigurable parallel processor using a plurality of chained memory ports

Reconfigurable parallel processor with a plurality of chained memory ports

Storage capability aware software defined storage

Processing system with interspersed processors with multi-layer interconnection

Static shared memory access with one piece of input data to be reused for successive execution of one instruction in a reconfigurable parallel processor

Technologies for fine-grained completion tracking of memory buffer accesses

Methods and apparatuses for copying a data page in an unmanaged flash memory device

Data buffer pointer fetching for direct memory access

MEMORY MODULE AND MEMORY SYSTEM INCLUDING THE SAME

Systems and methods for providing power-efficient file system operation to a non-volatile block memory

Integrated heterogeneous solid state storage drive

Transaction elimination using metadata

Shared resource access arbitration method, and shared resource access arbitration device and shared resource access arbitration system for performing same

Multiple linked list data structure

Allocation of memory buffers in computing system with multiple memory channels

Memory control device

Devices and methods for autonomous hardware management of circular buffers

Systems and methods for utilizing DDR-DRAM chips in hybrid DDR-DIMMs and for cascading DDR-DIMMs

HYBRID COMPUTING MODULE

Register read and write operations over auto negotiation next pages

Bus control circuit, information processing apparatus, and control method for bus control circuit

Firmware update of an interconnect device

Overflow region memory management

FILES ACCESS FROM A NVM TO EXTERNAL DEVICES THROUGH AN EXTERNAL RAM

Lock-free processing of stateless protocols over RDMA

Multi-channel DMA system with command queue structure supporting three DMA modes

Bus control device, relay device, and bus system

Hybrid LPDDR4-DRAM with cached NVM and flash-NAND in multi-chip packages for mobile devices

Column Bus Driving Method For Micro Display Device

COMPUTING MODULE WITH SERIAL DATA CONNECTIVITY

System and method for processing interrupts by processors of a microcontroller in a low-power mode

Computer program product, system, and method to allow a host and a storage device to communicate between different fabrics

Variable acquisition buffer length

High performance interconnect physical layer

Data processing

Bimodal PHY for low latency in high speed interconnects

Bus system and bus traffic control apparatus for controlling the same

APPARATUSES AND METHODS FOR TRAINING ONE OR MORE SIGNAL TIMING RELATIONS OF A MEMORY INTERFACE

DATA FLOW COMPUTATION USING FIFOS

Parallel processing apparatus and inter-node communication method

Data processing

Multi-channel memory operations based on bit error rates

Memory device performing near-data processing using a plurality of data processing engines that independently perform data processing operations, and system including the same

Efficient arbitration for memory accesses

Performing multiple write operations to a memory using a pending write queue/cache

INTERCONNECT NETWORK SUPPORTING MULTIPLE CONSISTENCY MECHANISMS, MULTIPLE PROTOCOLS, AND MULTIPLE SWITCHING MECHANISMS

Electronic control unit and data transmission method

Parsing, processing, and/or securing stream buffers

Server

Method and system for buffer state based low power operation in a MoCA network

System and method for memory access token reassignment

Methods for controlling data transfer speed of a data storage device and a host device utilizing the same

Semiconductor device and semiconductor integrated system

Uniform memory access architecture

Uniform memory access architecture

Deallocation of memory buffer in multiprocessor systems

Pre-allocating memory buffers by physical processor and using a bitmap metadata in a control program

Securing stream buffers

Pre-allocating memory buffers by physical processor and using a bitmap metadata in a control program

Adaptive routing for link-level retry protocol

Controller, memory system and operating method thereof