Hierarchical Mantissa Bit Length Selection For Hardware Implementation Of Deep Neural Network

Hierarchical Mantissa Bit Length Selection For Hardware Implementation Of Deep Neural Network

SYSTOLIC ARRAY WITH INPUT REDUCTION TO MULTIPLE REDUCED INPUTS

COMPUTER-IMPLEMENTED METHOD FOR TRANSFORMING A BIT STREAM INTO A FLOATING-POINT NUMBER

HIERARCHICAL MANTISSA BIT LENGTH SELECTION FOR HARDWARE IMPLEMENTATION OF DEEP NEURAL NETWORK

ADDITION METHOD, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE

SYSTEMS AND METHODS FOR PERFORMING DOUBLE PRECISION HIGH-SPEED ARITHMETIC OPERATION

MULTIPLIER-LESS CONVOLUTION BASED NEURAL PROCESSING UNIT AND METHOD OF OPERATING THE SAME

UNSIGNED INTEGER MULTIPLY-ACCUMULATE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS

METHOD FOR APPROXIMATIVELY DETERMINING A SCALAR PRODUCT USING A MATRIX CIRCUIT

METHODS, SYSTEMS, AND MEDIA FOR LOW-BIT NEURAL NETWORKS USING BIT SHIFT OPERATIONS

METHOD AND APPARATUS FOR MATRIX COMPUTATION USING DATA CONVERSION IN A COMPUTE ACCELERATOR

FRACTIONAL LOGARITHMIC NUMBER SYSTEM ADDER

Multiplier circuit

EFFICIENT LOOK-UP TABLE BASED FUNCTIONS FOR ARTIFICIAL INTELLIGENCE (AI) ACCELERATOR

Techniques, devices, and instruction set architecture for efficient modular division and inversion

Method and apparatus with bit-serial data processing of a neural network

FLOATING POINT FUSED MULTIPLY ADD WITH REDUCED 1'S COMPLEMENT DELAY

MULTI-PRECISION ARITHMETIC RIGHT SHIFT

FIXED BINARY ADDER WITH SMALL AREA AND METHOD OF DESIGNING THE SAME

METHODS AND SYSTEMS OF OPERATING A NEURAL CIRCUIT IN A NON-VOLATILE MEMORY BASED NEURAL-ARRAY

METHODS AND SYSTEMS OF OPERATING A NEURAL CIRCUIT IN A NON-VOLATILE MEMORY BASED NEURAL-ARRAY

SYSTEMS AND METHODS FOR ACCELERATING THE COMPUTATION OF THE EXPONENTIAL FUNCTION

METHODS AND SYSTEMS OF OPERATING A NEURAL CIRCUIT IN A NON-VOLATILE MEMORY BASED NEURAL-ARRAY

SYSTOLIC ARRAY WITH INPUT REDUCTION TO MULTIPLE REDUCED INPUTS

ARITHMETIC DEVICE, METHOD, AND PROGRAM

Compute-in-memory macro device and electronic device

METHOD AND NON-TRANSITORY COMPUTER READABLE MEDIUM FOR COMPUTE-IN-MEMORY MACRO ARRANGEMENT, AND ELECTRONIC DEVICE APPLYING THE SAME

Semiconductor device including multiplier circuit

Measurement transmission method enabling network loading to be reduced

Approximation of samples of a digital signal reducing a number of significant bits

Method and apparatus with data processing

Circuit and method for binary flag determination

Method, apparatus, and system for embedding information into probe data

Arithmetic processing apparatus, control method, and non-transitory computer-readable recording medium having stored therein control program

Arithmetic processing apparatus, control method, and non-transitory computer-readable recording medium having stored therein control program

Hexadecimal exponent alignment for binary floating point unit

Approximation of samples of a digital signal reducing a number of significant bits according to values of the samples

Addition method, semiconductor device, and electronic device

Overflow or underflow handling for anchored-data value

Apparatus for performing modal interval calculations based on decoration configuration

Methods and systems of operating a neural circuit in a non-volatile memory based neural-array

Methods and systems of implementing positive and negative neurons in a neural array-based flash memory

High performance merge sort with scalable parallelization and full-throughput reduction

Method for determining a value of an integer scaling in a linking of input sets to output sets, and computer program product

Apparatus for performing modal interval calculations based on decoration configuration

Operation processing apparatus, information processing apparatus and information processing method

Hierarchical mantissa bit length selection for hardware implementation of deep neural network

Method and apparatus with bit-serial data processing of a neural network

Microprocessor with dynamically adjustable bit width for processing data

Microprocessor for neural network computing and processing method of macroinstruction

Microprocessor with booth multiplication

Microprocessor with booth multiplication

Secure computation system, secure computation method, secure computation apparatus, distribution information generation apparatus, and methods and programs therefor

Apparatus for performing modal interval calculations based on decoration configuration

Apparatus and method for processing floating point values

Apparatus for performing modal interval calculations based on decoration configuration

Apparatus employing user-specified binary point fixed point arithmetic

Apparatus and method for performing conversion operation

Apparatus and method for performing conversion operation

Apparatus and method for vector processing

Vector operands with component representing different significance portions

Exception generation when generating a result value with programmable bit significance

Exponent monitoring

Significance alignment

Data processing apparatus and method using programmable significance data

Fast computation of products by dyadic fractions with sign-symmetric rounding errors

Multiplier circuit with dynamic energy consumption adjustment

Method, apparatus, system for single-path floating-point rounding flow that supports generation of normals/denormals and associated status flags

Arithmetic processing apparatus and an arithmetic processing method

Floating-point adder

Arithmetic circuit, arithmetic processing apparatus and method of controlling arithmetic circuit

Arithmetic circuit, arithmetic processing apparatus and method of controlling arithmetic circuit

System and method for testing whether a result is correctly rounded

EFFICIENT MULTIPLICATION TECHNIQUES

Enhanced precision sum-of-products calculation using high order bits register operand and respective low order bits cache entry

COMPUTATION OF JACOBIAN LOGARITHM OPERATION

Semiconductor integrated circuit and exponent calculation method

Method for carry estimation of reduced-width multipliers

Multiplier with Shifter

Arithmetic processing device and methods thereof

ARITHMETIC-LOGIC UNIT FOR DIGITAL SIGNAL PROCESSOR

Sine/cosine generator

Apparatus and method for optimizing the performance of x87 floating point addition instructions in a microprocessor

Dynamic range enhancement for arithmetic calculations in real-time control systems using fixed point hardware

Apparatus and method for low complexity combinatorial coding of signals

Fast computation of products by dyadic fractions with sign-symmetric rounding errors

MATRIX OPERATION DEVICE

Method for reducing round-off error in fixed-point arithmetic

System and method for implementing irregular data formats

Method for creating a representation of a calculation result linearly dependent upon a square of a value

Efficient encoding and access of mathematically precise variable precision numeric types

Controlled-precision iterative arithmetic logic unit

Method and a circuit using an associative calculator for calculating a sequence of non-associative operations

Calculation apparatus and storage medium in which calculation program is stored

Processing method and computer system for summation of floating point data

Floating-point processor with reduced power requirements for selectable subprecision

Rounding floating point division results

System and method for optimized reciprocal operations

Method and system for multiplier optimization

Method and apparatus for formatting numbers in microprocessors

Apparatus and method for reducing precision of data

Low-error fixed-width modified booth multiplier

High quality and high performance three-dimensional graphics architecture for portable handheld devices

Dynamic adjustment of floating point exponent bias for exponent compression

Circuit and method for compensating noise