PSEUDORANDOM NUMBER GENERATOR CIRCUIT

SATURATION LOGIC

Superscalar Execution Using Pipelines That Support Different Precisions

Floating-Point Data Precision Conversion Method and Apparatus

FUSED MULTIPLY-ADD (FMA) OPERATION USING OPERAND EXPONENT DIFFERENCES

RE-ROUNDING IN INTEGRATED CIRCUIT FOR VARIANCE REDUCTION IN AI OPERATIONS

REPRODUCIBLE STOCHASTIC ROUNDING FOR IN-NETWORK COMPUTING

MANTISSA ALIGNMENT WITH ROUNDING

REPRODUCIBLE FLOATING-POINT STOCHASTIC ROUNDING

MAC ARRAY AND HARDWARE ACCELERATOR INCLUDING THE SAME

DATA PROCESSING APPARATUS AND METHOD, ELECTRONIC DEVICE, AND STORAGE MEDIUM

PARALLEL DETERMINISTIC STOCHASTIC ROUNDING

METHOD AND SYSTEM FOR ROUNDING A SUBNORMAL NUMBER

FLOATING-POINT DECOMPOSITION CIRCUITRY WITH DYNAMIC PRECISION

MEMORY DEVICE FOR SUPPORTING MACHINE LEARNING, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF OPERATING THE SAME

GRAPHICS PROCESSORS

PROCESSING CORE WITH DATA ASSOCIATIVE ADAPTIVE ROUNDING

INSTRUCTIONS TO CONVERT FROM FP16 TO BF8

NEURAL NETWORK OPERATION APPARATUS AND METHOD

FLOATING-POINT DECOMPOSITION CIRCUITRY WITH DYNAMIC PRECISION

SOFTMAX FUNCTION APPROXIMATION CALCULATION DEVICE, APPROXIMATION CALCULATION METHOD, AND APPROXIMATION CALCULATION PROGRAM

COMPRESSION TECHNIQUES FOR VERTICES OF GRAPHIC MODELS

Apparatus for Calculating and Retaining a Bound on Error during Floating-Point Operations and Methods Thereof

Non-PLL, 1-wire, asynchronous oversampling of delta-sigma ADC bitstream

METHODS AND SYSTEMS EMPLOYING ENHANCED BLOCK FLOATING POINT NUMBERS

INPUT METHOD AND APPARATUS BASED ON SAMPLE-PROBABILITY QUANTIZATION, AND ELECTRONIC DEVICE

METHOD AND DEVICE FOR ROUNDING IN VARIABLE PRECISION COMPUTING

Decimal floating-point instruction in a round-for-reround mode

Rounding hexadecimal floating point numbers using binary incrementors

Processing core with data associative adaptive rounding

STOCHASTIC ROUNDING FOR NEURAL PROCESSOR CIRCUIT

MULTIPLICATION BY A RATIONAL IN HARDWARE WITH SELECTABLE ROUNDING MODE

METHOD AND APPARATUS FOR MEASURING WEIGHT OF DISCRETE ENTITY

Data prediction and proactive request system using artificial intelligence

METHOD AND APPARATUS FOR GENERATING FIXED-POINT QUANTIZED NEURAL NETWORK

Compression techniques for vertices of graphic models

MODEL TRAINING METHOD AND APPARATUS FOR FEDERATED LEARNING, DEVICE, AND STORAGE MEDIUM

Tininess detection

Apparatus and method for vector packed dual complex-by-complex and dual complex-by-complex conjugate multiplication

Compression in lattice-based cryptography

Vector convert hexadecimal floating point to scaled decimal instruction

COMPUTING APPARATUS, METHOD, BOARD CARD AND COMPUTER-READABLE STORAGE MEDIUM

Arithmetic operation device and arithmetic operation method

INSTRUCTIONS TO CONVERT FROM FP16 TO BF8

COMPUTING APPARATUS AND METHOD, BOARD CARD, AND COMPUTER READABLE STORAGE MEDIUM

Multiplier Circuit Array, MAC and MAC Pipeline including Same, and Methods of Configuring Same

METHOD FOR UPDATING AN ARTIFICIAL NEURAL NETWORK

System and method of generating quantum unitary noise using silicon based quantum dot arrays

SYSTEM AND METHOD OF QUANTUM STOCHASTIC ROUNDING USING SILICON BASED QUANTUM DOT ARRAYS

BIT-WIDTH OPTIMIZATION METHOD FOR PERFORMING FLOATING POINT TO FIXED POINT CONVERSION

High-precision anchored-implicit processing

ADAPTIVE QUANTIZATION METHOD AND APPARATUS, DEVICE AND MEDIUM

System and method for rounding reciprocal square root results of input floating point numbers

FLOATING POINT COMPUTATION FOR HYBRID FORMATS

Programmable Device Implementing Fixed and Floating Point Functionality in a Mixed Architecture

APPARATUS, METHOD, AND STORAGE MEDIUM

Repurposed hexadecimal floating point data path

Elimination of rounding error accumulation

DEEP NEURAL NETWORK OPERATION METHOD AND APPARATUS

Circuitry for floating-point power function

NEURAL NETWORK SECURITY

Neural network device for neural network operation, operating method of the neural network device, and application processor including the same

Encoding method and device, decoding method and device, and storage medium

Apparatus and method for double-precision ray traversal in a ray tracing pipeline

Methods to compress range doppler map (RDM) values from floating point to decibels (dB)

Processing core with data associative adaptive rounding

Performing Rounding Operations Responsive To An Instruction

ERROR-BOUND FLOATING POINT DATA COMPRESSION SYSTEM

Low latency floating-point division operations

Rounding circuitry for floating-point mantissas

Parallel rounding for conversion from binary floating point to binary coded decimal

Parallelized rounding for decimal floating point to binary coded decimal conversion

Repurposed hexadecimal floating point data path

Prepare for shorter precision (round for reround) mode in a decimal floating-point instruction

EFFICIENT ARTIFICIAL INTELLIGENCE ACCELERATOR

Floating point dot-product operator with correct rounding

Fused Multiply-Add operator for mixed precision floating-point numbers with correct rounding

Compression techniques for vertices of graphic models

Floating-point unit stochastic rounding for accelerated deep learning

Sorting device

Quantization device, quantization method, and recording medium

Mechanism to perform single precision floating point extended math operations

Systems and methods to perform floating-point addition with selected rounding

Alignment shifting and incrementing to determine a rounded result of adding first and second floating-point operands

Apparatus and method for rounding

Execution unit for evaluating functions using newton raphson iterations

INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND STORAGE MEDIUM

Floating-point decomposition circuitry with dynamic precision

WATER TIGHT RAY TRIANGLE INTERSECTION WITHOUT RESORTING TO DOUBLE PRECISION

Apparatus for calculating and retaining a bound on error during floating-point operations and methods thereof

ARITHMETIC PROCESSING APPARATUS AND CONTROLLING METHOD THEREFOR

Processing core with data associative adaptive rounding

Programmable device implementing fixed and floating point functionality in a mixed architecture

Integrated circuits with modular multiplication circuitry

Round for reround mode in a decimal floating point instruction

Multiply add functional unit capable of executing scale, round, getexp, round, getmant, reduce, range and class instructions

Block floating point computations using shared exponents

Very low precision floating point representation for deep learning acceleration

METHOD AND APPARATUS FOR PRE-ROUNDING IN A MULTIPLIER-ACCUMULATOR

Stochastic rounding logic

Compact arithmetic accelerator for data processing devices, systems and methods

Neural network processing unit including approximate multiplier and system on chip including the same

Floating-point number operation circuit and method

ARITHMETIC PROCESSING DEVICE AND ARITHMETIC PROCESSING METHOD

Round for reround mode in a decimal floating point instruction

Method and apparatus for generating fixed-point quantized neural network

Methods and apparatuses for calculating FP (full precision) and PP (partial precision) values

Compiler controls for program language constructs

Compiler controls for program language constructs

Reproducible stochastic rounding for out of order processors

Round for reround mode in a decimal floating point instruction

Reproducible stochastic rounding for out of order processors

Decimal and binary floating point rounding

Rounding circuitry and method

Performing Rounding Operations Responsive To An Instruction

Performing Rounding Operations Responsive To An Instruction

Performing Rounding Operations Responsive To An Instruction

Performing Rounding Operations Responsive To An Instruction

Constant fraction integer multiplication

Merged floating point operation using a modebit

Performing rounding operations responsive to an instruction

Performing rounding operations responsive to an instruction

Performing rounding operations responsive to an instruction

Stochastic rounding floating-point multiply instruction using entropy from a register

Stochastic rounding floating-point multiply instruction using entropy from a register

Multiply add functional unit capable of executing scale, round, getexp, round, getmant, reduce, range and class instructions

Round for reround mode in a decimal floating point instruction

Partial stochastic rounding that includes sticky and guard bits

Reproducible stochastic rounding for out of order processors

Floating point round-off amount determination processors, methods, systems, and instructions

Redundant representation of numeric value using overlap bits

Apparatus for calculating and retaining a bound on error during floating point operations and methods thereof

System and method for rounding reciprocal square root results of input floating point numbers

Neural network unit employing user-supplied reciprocal for normalizing an accumulated value

Neural network unit with shared activation function units

Neural processing unit that selectively writes back to neural memory either activation function output or accumulator value

Neural network unit with output buffer feedback and masking capability with processing unit groups that operate as recurrent neural network LSTM cells

Neural network unit that performs convolutions using collective shift register among array of neural processing units

Multi-operation neural network unit

Processor with hybrid coprocessor/execution unit neural network unit

Neural network unit with neural memory and array of neural processing units and sequencer that collectively shift row of data received from neural memory

Neural network unit with output buffer feedback for performing recurrent neural network computations

Neural network unit with neural processing units dynamically configurable to process multiple data sizes

Processor with architectural neural network execution unit

Tri-configuration neural network unit

Mechanism for communication between architectural program running on processor and non-architectural program running on execution unit of the processor regarding shared resource

Processor with variable rate execution unit

Direct execution by an execution unit of a micro-operation loaded into an architectural register file by an architectural instruction of a processor

Neural network unit with output buffer feedback and masking capability

Neural network unit with neural memory and array of neural processing units that collectively shift row of data received from neural memory

Apparatus employing user-specified binary point fixed point arithmetic

Neural network unit that performs stochastic rounding

Decimal and binary floating point rounding

Processing fixed and variable length numbers

Apparatus and method for controlling rounding when performing a floating point operation

Performing rounding operations responsive to an instruction

Decimal and binary floating point rounding

Floating-point arithmetic device, semiconductor device and information processing system

Multiplier unit with speculative rounding for use with division and square-root operations

Merged floating point operation using a modebit

Multiply add functional unit capable of executing SCALE, ROUND, GETEXP, ROUND, GETMANT, REDUCE, RANGE and CLASS instructions

Data processing apparatus and method for performing a narrowing-and-rounding arithmetic operation

Constant fraction integer multiplication

Conversion of a normalized n-bit value into a normalized m-bit value

Floating point round-off amount determination processors, methods, systems, and instructions

Method and apparatus for synthesising a sum of addends operation and an integrated circuit

Performing rounding operations responsive to an instruction

Merged floating point operation using a modebit

Apparatus and method for rounding a floating-point value to an integral floating-point value

ARITHMETIC CIRCUIT, ARITHMETIC PROCESSING APPARATUS AND METHOD OF CONTROLLING ARITHMETIC CIRCUIT

System and method of bypassing unrounded results in a multiply-add pipeline unit

Multiply add functional unit capable of executing scale, round, GETEXP, round, GETMANT, reduce, range and class instructions

Method for floating point round to integer operation

Efficient forcing of corner cases in a floating point rounder

System to implement floating point adder using mantissa, rounding, and normalization

SATURATION AND ROUNDING IN MULTIPLY-ACCUMULATE BLOCKS

Relaxed remainder constraints with comparison rounding

Method for controlling rounding modes in single instruction multiple data (SIMD) floating-point units

Fast correctly-rounding floating-point conversion

Rendering data visualization with minimal round-off error

Bridge fused multiply-adder circuit

Three-path fused multiply-adder circuit

Round for reround mode in a decimal floating point instruction

RECONFIGURABLE CIRCUIT

Performing rounding operations responsive to an instruction

Fast correctly rounding floating point conversion and identifying exceptional conversion

N-BIT 2's COMPLEMENT SYMMETRIC ROUNDING METHOD AND LOGIC FOR IMPLEMENTING THE SAME

Integer rounding operation

Controlled-precision iterative arithmetic logic unit

Rounding computing method and computing device therefor

Rounding of binary integers

Specialized processing block for programmable logic device

Efficient error-check and exact-check for Newton-Raphson divide and square-root operations

Method and system for performing quad precision floating-point operations in microprocessors

Performing rounding in an arithmetic operation

Digital signal processing device

Method and apparatus for formatting numbers in microprocessors

Rounding correction for add-shift-round instruction with dual-use source operand for DSP

Precision cordic processor

System and method for a floating point unit with feedback prior to normalization and rounding

System and method for a fused multiply-add dataflow with early feedback prior to rounding

Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point units

Decimal rounding mode which preserves data information for further rounding to less precision

Method and system of achieving integer division by invariant divisor using N-bit multiply-add operation

Method and system to implement an improved floating point adder with integrated adding and rounding

Saturation and rounding in multiply-accumulate blocks

Low-error fixed-width modified booth multiplier

System and method for precise calculation of alternative units of measure

High performance implementation of exponent adjustment in a floating point design

Method and device for floating-point multiplication, and corresponding computer-program product

Random carry-in for floating-point operations

Superscalar execution using pipelines that support different precisions

Systolic array with output rounding for multiple source/destination data type pairs

Systolic array with output rounding across multiple data streams

Apparatus for calculating and retaining a bound on error during floating-point operations and methods thereof

Large-scale computations using an adaptive numerical format

Programmable device implementing fixed and floating point functionality in a mixed architecture

Specialized processing block with fixed- and floating-point structures