189525 ⎘
Methods or arrangements for processing data by operating upon the order or content of the data handled; Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices; Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using selection between two conditionally calculated carry or sum values
SIGNED EXTENSION CARRY-LOOK-AHEAD FOR ACCUMULATOR WITH BIT WIDTH DIFFERENCE
#2SIGNED EXTENSION CARRY-LOOK-AHEAD FOR ACCUMULATOR WITH BIT WIDTH DIFFERENCE
#3METHOD AND APPARATUS FOR OPERATING MEMORY PROCESSOR
#4ADDER WITH FIRST AND SECOND ADDER CIRCUITS FOR NON-POWER OF TWO INPUT WIDTH
#5FLOATING POINT FUSED MULTIPLY ADD WITH REDUCED 1'S COMPLEMENT DELAY
#6PARALLEL COMPUTATION OF A LOGIC OPERATION, INCREMENT, AND DECREMENT OF ANY PORTION OF A SUM
#7Split and duplicate ripple circuits
#8Arithmetic logic unit design in column analog to digital converter with shared gray code generator for correlated multiple samplings
#9Split and duplicate ripple circuits
#10Extendable multiple-digit base-2in-memory adder device
#11ARITHMETIC PROCESSING DEVICE
#12Systems and methods for low latency modular multiplication
#13Domino full adder based on delayed gating positive feedback
#14Memristor-based dividers using memristors-as-drivers (MAD) gates
#15Operation processing device, information processing device, and information processing method
#16Memristor-based multipliers using memristors-as-drivers (MAD) gates
#17Memristor-based dividers using memristors-as-drivers (MAD) gates
#18Apparatus and methods for vector operations
#19Apparatus and methods for vector operations
#20Apparatus and methods for vector operations
#21Memristor-based dividers using memristors-as-drivers (MAD) gates
#22Apparatus and methods for vector operations
#23Apparatus and methods for vector operations
#24Memristor-based multipliers using memristors-as-drivers (MAD) gates
#25Apparatus and methods for vector operations
#26Apparatus and methods for vector operations
#27Apparatus and methods for vector operations
#28Lookup table sharing for memory-based computing
#29Lookup table sharing for memory-based computing
#30Adder decoder
#31Apparatus and method for performing conversion operation
#32Apparatus and method for performing conversion operation
#33Apparatus and method for vector processing
#34Vector operands with component representing different significance portions
#35Exception generation when generating a result value with programmable bit significance
#36Exponent monitoring
#37Significance alignment
#38Data processing apparatus and method using programmable significance data
#39Binary adder and multiplier circuit
#40Adder capable of supporting addition and subtraction of up to n-bit data and method of supporting addition and subtraction of a plurality of data type using the adder
#41HYBRID ADDER USING DYNAMIC AND STATIC CIRCUITS
#42List structure control circuit
#43M-bit race delay adder and method of operation
#44STATIC LOGIC LING ADDER
#45Configurable hybrid adder circuitry
#46Address generating circuit and semiconductor memory device
#47METHOD TO PERFORM A SUBTRACTION OF TWO OPERANDS IN A BINARY ARITHMETIC UNIT PLUS ARITHMETIC UNIT TO PERFORM SUCH A METHOD
#48System and method for providing a double adder for decimal floating point operations
#49CARRY-SELECT ADDER
#50METHOD TO PERFORM A SUBTRACTION OF TWO OPERANDS IN A BINARY ARITHMETIC UNIT PLUS ARITHMETIC UNIT TO PERFORM SUCH A METHOD
#51Carry-select adder structure and method to generate orthogonal signal levels
#52Hybrid arithmetic logic unit
#53Sparse tree adder circuit
#54System and method for providing a double adder for decimal floating point operations
#55Mixed-type adder comprising multiple sub-adders having different carry propagation schemes
#56Apparatus and method for an address generation circuit
#57Arithmetic unit
#58Recursive carry-select topology in incrementer designs
#59Digital circuit
#60Addition circuit
#61Technique for generating output states in a security algorithm
#62Adder circuit with sense-amplifier multiplexer front-end
#63Adder, multiplier and integrated circuit
#64Arithmetic unit for addition or subtraction with preliminary saturation detection
#65Secure multi-party computation and communication
#66Secure multi-party computation and communication
#67Memristor-based adders using memristors-as-drivers (MAD) gates
#68Memristor-based adders using memristors-as-drivers (MAD) gates