189524 ⎘
Methods or arrangements for processing data by operating upon the order or content of the data handled; Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices; Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
Sub-classes:NEW LOW POWER ADDER TREE STRUCTURE
#2ANALOG COMPUTATION OF SHIFT AND ADD FOR DOT PRODUCT ENGINES
#3LARGE INTEGER MULTIPLICATION ENHANCEMENTS FOR GRAPHICS ENVIRONMENT
#4HIGH SPEED RIPPLE ADDER
#5BIGNUM ADDITION AND/OR SUBTRACTION WITH CARRY PROPAGATION
#6Large integer multiplication enhancements for graphics environment
#7NEW LOW POWER ADDER TREE STRUCTURE
#8Adder circuitry for very large integers
#9Parallel-prefix adder and method
#10Parallel-prefix adder and method
#11In-memory full adder
#12FPGA logic cell with improved support for counters
#13Arithmetic logic unit for single-cycle fusion operations
#14Arithmetic logic unit for single-cycle fusion operations
#15Adder circuitry for very large integers
#16Prefix network-directed addition
#17Energy-efficient variable power adder and methods of use thereof
#18Apparatus and method for performing conversion operation
#19Apparatus and method for performing conversion operation
#20Apparatus and method for vector processing
#21Vector operands with component representing different significance portions
#22Exception generation when generating a result value with programmable bit significance
#23Exponent monitoring
#24Significance alignment
#25Data processing apparatus and method using programmable significance data
#26Apparatus, method and program for calculating the result of a repeating iterative sum
#27Configurable IC's with large carry chains
#28Data processing apparatus and method for performing a narrowing-and-rounding arithmetic operation
#29Single-pass parallel prefix scan with dynamic look back
#30Generating a fast 3x multiplicand term for radix-8 booth multiplication
#31Arithmetic circuit and arithmetic method
#32Three-term predictive adder and/or subtracter
#33Parallel self-timed adder (PASTA)
#34Configurable IC's with large carry chains
#35Three-term predictive adder and/or subtracter
#36HYBRID ADDER USING DYNAMIC AND STATIC CIRCUITS
#37Techniques for use with automated circuit design and simulations
#38Look up table (LUT) structure supporting exclusive or (XOR) circuitry configured to allow for generation of a result using quaternary adders
#39Methods and apparatus for sum of address compare write recode and compare reduction
#40System and method of using common adder circuitry for both a horizontal minimum instruction and a sum of absolute differences instruction
#41Configurable IC'S with large carry chains
#42Address generation unit with pseudo sum to accelerate load/store operations
#43Flexible carry scheme for field programmable gate arrays
#44Macrocell and method for adding
#45Interconnection and input/output resources for programmable logic integrated circuit devices
#46Flexible adder circuits with fast carry chain circuitry
#47N-BIT ADDER AND CORRESPONDING ADDITION METHOD
#48System, method, and computer program product for performing a scan operation on a sequence of single-bit values using a parallel processor architecture
#49Techniques for use with automated circuit design and simulations
#50Interconnection and input/output resources for programmable logic integrated circuit devices
#51Conditional Selection Adder and Method of Conditional Selection Adding
#52Binary coded decimal addition
#53Cyclic segmented prefix circuits for mesh networks
#54Configurable IC with configurable routing resources that have asymmetric input and/or outputs
#55Configurable IC with large carry chains
#56Configurable IC's with dual carry chains
#57Configurable IC's with carry bypass circuitry
#58Configurable IC's with configurable logic circuits that perform adder and/or subtractor operations
#59Interconnection resources for programmable logic integrated circuit devices
#60Interconnection and input/output resources for programmable logic integrated circuit devices
#61Mixed-type adder comprising multiple sub-adders having different carry propagation schemes
#62Carry-skip adder having merged carry-skip cells with sum cells
#63Efficient circuits for out-of-order microprocessors
#64Interconnection resources for programmable logic integrated circuit devices
#65Arithmetic circuit with balanced logic levels for low-power operation
#66Adder-subtracter circuit
#67Logic circuit
#68Adder
#69Addition circuit
#70Adder structure with midcycle latch for power reduction
#71Adder circuit with sense-amplifier multiplexer front-end
#72Binary coded decimal addition
#73Calculating unit and method for subtracting
#74Semiconductor circuit for arithmetic processing and arithmetic processing method
#75Process for designing comparators and adders of small depth
#76Compaction of multiplier and adder circuits
#77High spurious-free dynamic-range line driver