Enhanced performance-aware instruction scheduling

METHOD AND APPARATUS FOR FLUSHING INSTRUCTIONS FROM RESERVATION STATIONS

SELECT IN-ORDER INSTRUCTION PICK USING AN OUT OF ORDER INSTRUCTION PICKER

PROVIDING CODE SECTIONS FOR MATRIX OF ARITHMETIC LOGIC UNITS IN A PROCESSOR

Data read-write scheduler and reservation station for vector operations

Data read-write scheduler and reservation station for vector operations

Entanglement of pages and guest threads

Apparatus and methods for matrix multiplication

Token-based data dependency protection for memory access

Instruction and logic for tracking fetch performance bottlenecks

Efficient mitigation of side-channel based attacks against speculative execution processing architectures

Flash Storage Devices Executing ECC in Parallel and Methods Thereof

Memory device, a dual inline memory module, a storage device, an apparatus for storing, a method for storing, a computer program, a machine readable storage, and a machine readable medium

Wide vector execution in single thread mode for an out-of-order processor

Wide vector execution in single thread mode for an out-of-order processor

Managing an issue queue for fused instructions and paired instructions in a microprocessor

Managing an issue queue for fused instructions and paired instructions in a microprocessor

Processor with hybrid pipeline capable of operating in out-of-order and in-order modes

TECHNIQUES TO MITIGATE HIGH LATENCY INSTRUCTIONS IN HIGH FREQUENCY EXECUTION PATHS

Fast multi-width instruction issue in parallel slice processor

Parallel slice processor shadowing states of hardware threads across execution slices

Dual data streams sharing dual level two cache access ports to maximize bandwidth utilization

CACHE RETURN ORDER OPTIMIZATION

Cache return order optimization

Cracked execution of move-to-FPSCR instructions

Managing backend resources via frontend steering or stalls

Vector processing using loops of dynamic vector length

Stream processor with decoupled crossbar for cross lane operations

Instructions for remote atomic operations

System and method of merging partial write results for resolving renaming size issues

Selective updating of floating point controls

Efficient enforcement of barriers with respect to memory move sequences

Asymmetric multi-core heterogeneous parallel processing system

Scheduling tasks using work fullness counter

Scheduling tasks using targeted pipelines

Scheduling tasks using swap flags

Systems and methods for automatic computer code parallelization

Multicore on-die memory microcontroller

Continuation analysis tasks for GPU task scheduling

Performance scaling for binary translation

Arithmetic processing device and method of controlling arithmetic processing device

Virtual machine coprocessor for accelerating software execution

Multifunction vector processor circuits

Tensor processor instruction set architecture

On-demand GPR ECC error detection and scrubbing for a multi-slice microprocessor

Linkable issue queue parallel execution slice processing method

Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries

Implementing barriers to efficiently support cumulativity in a weakly ordered memory system

Banking register renaming to reduce power

MULTI-NULLIFICATION

System and method for processing and arbitrating submission and completion queues

Processing operation issue control

Intelligent thread dispatch and vectorization of atomic operations

Techniques for comprehensively synchronizing execution threads

Mixed inference using low and high precision

Instructions having support for floating point and integer data types in the same register

System and method of reducing processor pipeline stall caused by full load queue

Early predicate look-up

Enhancing processing performance of artificial intelligence/machine hardware by data sharing and distribution as well as reuse of data in neuron buffer/line buffer

Dynamically partitioning workload in a deep neural network module to reduce power consumption

Power-efficient deep neural network module configured for parallel kernel and parallel input processing

Power-efficient deep neural network module configured for executing a layer descriptor list

Minimizing memory reads and increasing performance by leveraging aligned blob data in a processing unit of a neural network environment

Neural network processor using compression and decompression of activation data to reduce memory bandwidth utilization

Reducing power consumption in a neural network processor by skipping processing operations

Power-efficient deep neural network module configured for layer and operation fencing and dependency management

Dynamic sequencing of data partitions for optimizing memory utilization and performance of neural networks

Control system for process data and method for controlling process data

Predicting cache misses using data access behavior and instruction address

SYSTEM AND METHOD OF EXECUTING CACHE LINE UNALIGNED LOAD INSTRUCTIONS

Graphics processing integrated circuit package

Operation of a multi-slice processor with an expanded merge fetching queue

Engine to enable high speed context switching via on-die storage

Parallel input/output via multipath software

Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices

Method of detecting repetition of an out-of-order execution schedule, apparatus and computer-readable medium

Processor and task processing method therefor, and storage medium

Hints for shared store pipeline and multi-rate targets

Determine whether to fuse move prefix instruction and immediately following instruction independently of detecting identical destination registers

Spin loop delay instruction

Apparatus and method to generate trace data in response to transactional execution

Spin loop delay instruction

Operation instruction response control method and terminal for human-machine interface

Resource scheduling system and method under graphics processing unit virtualization based on instant feedback of application effect

Multifunctional hexadecimal instruction form system and program product

Hardware mechanism to mitigate stalling of a processor core

Indicating instruction scheduling mode for processing wavefront portions

Method and apparatus for providing accelerated access to a memory system

Method and apparatus for efficient scheduling for asymmetrical execution units

Hardware processors and methods for tightly-coupled heterogeneous computing

METHOD FOR POPULATING AND INSTRUCTION VIEW DATA STRUCTURE BY USING REGISTER TEMPLATE SNAPSHOTS

Infinite processor thread balancing

Method and apparatus for asynchronous scheduling

Parallel slice processor shadowing states of hardware threads across execution slices

Data processing systems

IMPLEMENTATION OF REGISTER RENAMING, CALL-RETURN PREDICTION AND PREFETCH

Load/store unit for a processor, and applications thereof

Unambiguous proxying of interface methods

Methods and apparatus for adjacency network delivery of operands to instruction specified destinations that reduces storage of temporary variables

Issuing instructions to multiple execution units

DISPATCH OF PROCESSOR READ RESULTS

Operation cache

General purpose register allocation in streaming processor

Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines

Bufferless communication for redundant multithreading using register permutation

Deterministic code fingerprinting for program flow monitoring

Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction

Hardware acceleration method, compiler, and device

Pipeline including separate hardware data paths for different instruction types

Computer instruction processing method, coprocessor, and system

Compact linked-list-based multi-threaded instruction graduation buffer

Accessing data in multi-dimensional tensors

Method, device, and single-tasking system for implementing multi-tasking in single-tasking system

Computer architecture with a hardware accumulator reset

System and method for load balancing in out-of-order clustered decoding

Method and system for managing data access in storage system

Electronic apparatus, processor and control method including a compiler scheduling instructions to reduce unused input ports

Reducing power consumption in a multi-slice computer processor

Processor with improved alias queue and store collision detection to reduce memory violations and load replays

Effectiveness and prioritization of prefetches

Arithmetic processing device and control method for arithmetic processing device

Reducing power consumption in a multi-slice computer processor

Multi-thread processor with rescheduling when threads are nondispatchable

Independent mapping of threads

Signaling interface with phase and framing calibration

Method for implementing a reduced size register view data structure in a microprocessor

Memory dependence prediction

Efficient enforcement of barriers with respect to memory move sequences

System and method for load and store queue allocations at address generation time

Highly efficient inexact computing storage device

Starting and stopping instruction dispatch to execution unit queues in a multi-pipeline processor

Microprocessor that fuses if-then instructions

Scheduling independent and dependent operations for processing

Controlling the operating speed of stages of an asynchronous pipeline

Method for performing dual dispatch of blocks and half blocks

Method for executing multithreaded instructions grouped into blocks

Techniques for hybrid computer thread creation and management

Advanced processor architecture

OPERATION OF A MULTI-SLICE PROCESSOR IMPLEMENTING PRIORITIZED DEPENDENCY CHAIN RESOLUTION

Effectiveness and prioritization of prefeteches

PROGRAM INFORMATION GENERATION SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT

LOAD-STORE QUEUE FOR MULTIPLE PROCESSOR CORES

LOAD-STORE QUEUE FOR BLOCK-BASED PROCESSOR

Core pairing in multicore systems

Techniques for hybrid computer thread creation and management

INSTRUCTION AND LOGIC TO PROVIDE VECTOR SCATTER-OP AND GATHER-OP FUNCTIONALITY

Broadcasting messages between execution slices for issued instructions indicating when execution results are ready

Executing memory requests out of order

Operation of a multi-slice processor implementing datapath steering

Operation of a multi-slice processor implementing datapath steering

Fetched data in an ultra-short piped load store unit

System and method for associative power and clock management with instruction governed operation for power efficient computing

Direct register restore mechanism for distributed history buffers

Operation of a multi-slice processor implementing tagged geometric history length (TAGE) branch prediction

Method and apparatus for reordering in a non-uniform compute device

Graphic processor unit providing reduced storage costs for similar operands

Age based fast instruction issue

Implementing barriers to efficiently support cumulativity in a weakly-ordered memory system

Implementing barriers to efficiently support cumulativity in a weakly-ordered memory system

Hybrid block-based processor and custom function blocks

Out-of-order block-based processors and instruction schedulers using ready state data indexed by instruction position identifiers

Incremental scheduler for out-of-order block ISA processors

PARALLEL INSTRUCTION SCHEDULER FOR BLOCK ISA PROCESSOR

Merging status and control data in a reservation station

Sliding time window control mechanism for parallel execution of multiple processor core models in a virtual platform simulation

Annotation logic for dynamic instruction lookahead distance determination

FPSCR STICKY BIT HANDLING FOR OUT OF ORDER INSTRUCTION EXECUTION

Method, apparatus and instructions for parallel data conversions

Method and apparatus for implementing a dynamic out-of-order processor pipeline

Preventing hazard flushes in an instruction sequencing unit of a multi-slice processor

ARITHMETIC PROCESSING DEVICE, METHOD, AND SYSTEM

Execution slice with supplemental instruction port for an instruction using a source operand from another instruction port

Operation of a multi-slice processor implementing a hardware level transfer of an execution thread

APPARATUS AND METHOD FOR RE-EXECUTION OF FAULTING OPERATIONS

Multiple instruction issuance with parallel inter-group and intra-group picking

Executing a composite VLIW instruction having a scalar atom that indicates an iteration of execution

Apparatus and method for dynamic power reduction in a unified scheduler

Operation of a multi-slice processor with an expanded merge fetching queue

Relaxed execution of overlapping mixed-scalar-vector instructions

Age based fast instruction issue

Preventing premature reads from a general purpose register

Command scheduler for a display device

Single cycle multi-branch prediction including shadow cache for early far branch prediction

Controlling transition between using first and second processing circuitry

Thread migration using a microcode engine of a multi-slice processor

Coalescing adjacent gather/scatter operations

Operation of a multi-slice processor preventing early dependent instruction wakeup

Operation of a multi-slice processor implementing dynamic switching of instruction issuance order

Energy efficient processor core architecture for image processor

Dual data streams sharing dual level two cache access ports to maximize bandwidth utilization

Dynamic pipeline throttling using confidence-based weighting of in-flight branch instructions

System and method for contextual vectorization of instructions at runtime

Systems, apparatuses, and methods for performing a double blocked sum of absolute differences

Instructions for managing a parallel cache hierarchy

Operation of a multi-slice processor implementing a mechanism to overcome a system hang

Parallel dispatching of multi-operation instructions in a multi-slice computer processor

Controlling processing of instructions in a processing pipeline

Controlling processing of instructions in a processing pipeline

Asynchronous instruction execution apparatus with execution modules invoking external calculation resources

MFENCE AND LFENCE MICRO-ARCHITECTURAL IMPLEMENTATION METHOD AND SYSTEM

Execution of load instructions in a processor

Predictive fetching and decoding for selected instructions

Allocating a register to an instruction using register index information

Providing task-triggered deterministic operational mode for simultaneous multi-threaded superscalar processor

Scheduling execution of instructions on a processor having multiple hardware threads with different execution resources

Techniques for hybrid computer thread creation and management

Techniques for hybrid computer thread creation and management

INSTRUCTION EXECUTION METHOD AND PROCESSOR

Computer system

Lightweight interrupts for condition checking

Method and apparatus for detecting memory conflicts using distinguished memory addresses

Processing of multiple instruction streams in a parallel slice processor

Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor

Multi-slice processor issue of a dependent instruction in an issue queue based on issue of a producer instruction

Multi-slice processor issue of a dependent instruction in an issue queue based on issue of a producer instruction

Energy efficient source operand issue

Operation of a multi-slice processor with reduced flush and restore latency

Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor

Operation of a multi-slice processor with reduced flush and restore latency

Reducing power consumption in a multi-slice computer processor

Reducing power consumption in a multi-slice computer processor

Multilevel conversion table cache for translating guest instructions to native instructions

Processor with an expandable instruction set architecture for dynamically configuring execution resources

Run-time code parallelization with independent speculative committing of instructions per segment

Conversion system for a processor with an expandable instruction set architecture for dynamically configuring execution resources

Compiler system for a processor with an expandable instruction set architecture for dynamically configuring execution resources

Instruction And Logic For Programmable Fabric Hierarchy And Cache

System and method of speculative parallel execution of cache line unaligned load instructions

Cache system and method using track table and branch information

Computer architecture with resistive processing units

Fusion of instructions by delaying handling of a partial subset of a fusible group of instructions

Method for dependency broadcasting through a source organized source view data structure

Method for populating register view data structure by using register template snapshots

Method for populating a source view data structure by using register template snapshots

Tightly coupled processor arrays using coarse grained reconfigurable architecture with iteration level commits

Tightly coupled processor arrays using coarse grained reconfigurable architecture with iteration level commits

Method for forming constant extensions in the same execute packet in a VLIW processor

Multi-thread processor with rescheduling when threads are nondispatchable

Data processing apparatus and method for executing a stream of instructions out of order with respect to original program order

Processing instructions in parallel with waw hazards and via a distributed history buffer in a microprocessor having a multi-execution slice architecture

SIMD variable shift and rotate using control manipulation

Neural network unit employing user-supplied reciprocal for normalizing an accumulated value

Neural network unit with shared activation function units

Neural processing unit that selectively writes back to neural memory either activation function output or accumulator value

Neural network unit with output buffer feedback and masking capability with processing unit groups that operate as recurrent neural network LSTM cells

Neural network unit that performs convolutions using collective shift register among array of neural processing units

Multi-operation neural network unit

Processor with hybrid coprocessor/execution unit neural network unit

Neural network unit with neural memory and array of neural processing units and sequencer that collectively shift row of data received from neural memory

Neural network unit with output buffer feedback for performing recurrent neural network computations

Neural network unit with neural processing units dynamically configurable to process multiple data sizes

Processor with architectural neural network execution unit

Tri-configuration neural network unit

Mechanism for communication between architectural program running on processor and non-architectural program running on execution unit of the processor regarding shared resource

Processor with variable rate execution unit

System and method for predicting latency of a variable-latency instruction

Direct execution by an execution unit of a micro-operation loaded into an architectural register file by an architectural instruction of a processor

Variable length execution pipeline

Neural network unit with output buffer feedback and masking capability

Neural network unit with neural memory and array of neural processing units that collectively shift row of data received from neural memory

Neural network unit that performs stochastic rounding

System and method for managing static divergence in a SIMD computing architecture

Chained split execution of fused compound arithmetic operations

Instruction and Logic for Indirect Accesses

Microprocessor with a reservation stations structure including primary and secondary reservation stations and a bypass system

Reconfiguring execution pipelines of out-of-order (OOO) computer processors based on phase training and prediction

Debug support for block-based processor

Instruction block address register

Prefetching instruction blocks

Broadcast channel architectures for block-based processors

Block-based processor including topology and control registers to indicate resource sharing and size of logical processor

Multi-nullification

Write nullification

Store nullification in the target field

Implicit program order

Register read/write ordering

Dynamic generation of null instructions

Generation and use of memory access instruction order encodings

Multimodal targets in a block-based processor

Dense read encoding for dataflow ISA

Distinct system registers for logical processors

Block-based processor core composition register

Initiating instruction block execution using a register access instruction

Task execution in a SIMD processing unit with parallel groups of processing lanes

Multiple scheduling schemes for handling read requests

Fine-grained heterogeneous computing

Allocation of a segmented interconnect to support the execution of instruction sequences by a plurality of engines

Expedited servicing of store operations in a data processing system

Method of dispatching instruction data when a number of available resource credits meets a resource requirement

Handling Instruction Data and Shared resources in a Processor Having an Architecture Including a Pre-Execution Pipeline and a Resource and a Resource Tracker Circuit Based on Credit Availability

System and method of accelerating arbitration by approximating relative ages

Device and processing architecture for resolving execution pipeline dependencies without requiring no operation instructions in the instruction memory

Fusible instructions and logic to provide or-test and and-test functionality using multiple test sources

Techniques for implementing barriers to efficiently support cumulativity in a weakly-ordered memory system

Techniques for enhancing progress for hardware transactional memory

Computer with hybrid Von-Neumann/dataflow execution architecture

System and method for variable lane architecture

Age based fast instruction issue

Method and device for allocating a VLIW instruction based on slot information stored in a database by a calculation allocation instruction

Method and apparatus for implementing dynamic portbinding within a reservation station