Execution of micro-operations

Method and system for processing interrupts with shadow units in a microcontroller

Variable latency pipe for interleaving instruction tags in a microprocessor

Variable latency pipe for interleaving instruction tags in a microprocessor

Multicore system for fusing instructions queued during a dynamically adjustable time window

Instruction block allocation

Techniques to wake-up dependent instructions for back-to-back issue in a microprocessor

Techniques to wake-up dependent instructions for back-to-back issue in a microprocessor

Age-based management of instruction blocks in a processor instruction window

Explicit instruction scheduler state information for a processor

Bulk allocation of instruction blocks to a processor instruction window

Mapping instruction blocks based on block size

Reuse of decoded instructions

Decoupled processor instruction window and operand buffer

Instruction and logic for tracking fetch performance bottlenecks

TECHNIQUES FOR IMPROVING ISSUE OF INSTRUCTIONS WITH VARIABLE LATENCIES IN A MICROPROCESSOR

Data processing

Data processing

Mechanism to preclude load replays dependent on fuse array access in an out-of-order processor

Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor

Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor

Controlling execution of instructions for a processing pipeline having first out-of order execution circuitry and second execution circuitry

Arithmetic processing device and processing method of arithmetic processing device

Instruction and logic to perform dynamic binary translation

Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processor

Apparatus and method to preclude load replays dependent on write combining memory space access in an out-of-order processor

Apparatus and method to preclude non-core cache-dependent load replays in an out-of-order processor

Mechanism to preclude load replays dependent on long load cycles in an out-of-order processor

Load replay precluding mechanism

Mechanism to preclude uncacheable-dependent load replays in out-of-order processor

Thermal availability based instruction assignment for execution

Mechanism to preclude shared RAM-dependent load replays in an out-of-order processor

Apparatus and method for a hybrid latency-throughput processor

Multi-threaded processor interrupting and saving execution states of complex instructions of a first thread to allow execution of an oldest ready instruction of a second thread

Interconnect system to support the execution of instruction sequences by a plurality of partitionable engines

Method and apparatus to avoid deadlock during instruction scheduling using dynamic port remapping

Processing queue management

Energy efficient processor core architecture for image processor

Techniques for facilitating cracking and fusion within a same instruction group

Techniques for facilitating cracking and fusion within a same instruction group

Branch prediction with power usage prediction and control

Method and apparatus for performing an efficient scatter

Method and apparatus for a self-clocked, event triggered superscalar processor

Speculative load issue

Electronic circuit, arithmetic processing control method, program, and multi-core processor

Determining whether a flow is to be added to a network

APPARATUSES AND METHODS TO SELECTIVELY EXECUTE A COMMIT INSTRUCTION

Systems, methods, and apparatuses for resource monitoring

Multifunctional hexadecimal instruction form system and program product

Instruction and logic for scheduling instructions

System and method of reissue parking for a microprocessor

Instruction and logic to provide vector linear interpolation functionality

Parallelized multiple dispatch system and method for ordered queue arbitration

Register renaming in block-based instruction set architecture

Concurrent execution of heterogeneous vector instructions

PATH SELECTION BASED ACCELERATION OF CONDITIONALS IN COARSE GRAIN RECONFIGURABLE ARRAYS (CGRAS)

Instruction and logic for a binary translation mechanism for control-flow security

Techniques for hybrid computer thread creation and management

Delayed allocation of an out-of-order queue entry and based on determining that the entry is unavailable, enable deadlock avoidance involving reserving one or more entries in the queue, and disabling deadlock avoidance based on expiration of a predetermined amount of time

Load queue entry reuse for operand store compare history table update

Load queue entry reuse for operand store compare history table update

Dynamic assignment across dispatch pipes of source ports to be used to obtain indication of physical registers

Vector processor to operate on variable length vectors with out-of-order execution

Monolithic vector processor configured to operate on variable length vectors using a vector length register

Vector processor configured to operate on variable length vectors using implicitly typed instructions

Vector processor to operate on variable length vectors using graphics processing instructions

Vector processor configured to operate on variable length vectors with asymmetric multi-threading

Processor with hybrid pipeline capable of operating in out-of-order and in-order modes

Concurrent multiple instruction issued of non-pipelined instructions using non-pipelined operation resources in another processing core

Method and apparatus for operating a self-timed parallelized multi-core processor

Vector processor configured to operate on variable length vectors using instructions to combine and split vectors

Vector processor configured to operate on variable length vectors using instructions that change element widths

Vector processor configured to operate on variable length vectors using digital signal processing instructions

Extensible execution unit interface architecture with multiple decode logic and multiple execution units

Extensible execution unit interface architecture with multiple decode logic and multiple execution units

Vector processor configured to operate on variable length vectors using one or more complex arithmetic instructions

Handling operating system (OS) transitions in an unbounded transactional memory (UTM) mode

Buffering instructions of a single branch, backwards short loop within a virtual loop buffer

Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines

High performance processor system and method based on general purpose units

Local instruction loop buffer utilizing execution unit register file

Local instruction loop buffer utilizing execution unit register file

Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines

Power saving mechanism to reduce load replays in out-of-order processor

INTEGRATED FRAMEWORK OF MEMORY STORAGE MODULE AND SENSOR MODULE

Linkable issue queue parallel execution slice for a processor

PARALLEL SLICE PROCESSING METHOD USING A RECIRCULATING LOAD-STORE QUEUE FOR FAST DEALLOCATION OF ISSUE QUEUE ENTRIES

Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries

Pipelining out-of-order instructions

Instruction and logic for register based hardware memory renaming

INSTRUCTION AND LOGIC TO PERFORM A VECTOR SATURATED DOUBLEWORD/QUADWORD ADD

Instruction and logic for shift-sum multiplier

Apparatus and method for programmable load replay preclusion

Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processor

Power saving mechanism to reduce load replays in out-of-order processor

Mechanism to preclude load replays dependent on long load cycles in an out-of-order processor

Mechanism to preclude load replays dependent on page walks in an out-of-order processor

Load replay precluding mechanism

Mechanism to preclude uncacheable-dependent load replays in out-of-order processor

Mechanism to preclude I/O-dependent load replays in an out-of-order processor

Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines

Processor with a full instruction set decoder and a partial instruction set decoder

Generating design structure for microprocessor with arithmetic logic units and an efficiency logic unit

Structure for microprocessor including arithmetic logic units and an efficiency logic unit

Chip-to-chip signaling link timing calibration

Computer architecture with a hardware accumulator reset

Loop vectorization methods and apparatus

Device and method for scheduling multiple thread groups on SIMD lanes upon divergence in a single thread group

Coalescing adjacent gather/scatter operations

Nontransactional store instruction

PROCESSING METHOD INCLUDING PRE-ISSUE LOAD-HIT-STORE (LHS) HAZARD PREDICTION TO REDUCE REJECTION OF LOAD INSTRUCTIONS

Processor core including pre-issue load-hit-store (LHS) hazard prediction to reduce rejection of load instructions

Flexible instruction execution in a processor pipeline

Flexible instruction execution in a processor pipeline

Coalescing adjacent gather/scatter operations

Coalescing adjacent gather/scatter operations

Coalescing adjacent gather/scatter operations

Coalescing adjacent gather/scatter operations

Coalescing adjacent gather/scatter operations

Coalescing adjacent gather/scatter operations

Coalescing adjacent gather/scatter operations

Compressing instruction queue for a microprocessor

Independent mapping of threads

Coprocessor for out-of-order loads

Variable length execution pipeline

Method and apparatus for improved thread selection

Dynamic issue masks for processor hang prevention

Independent mapping of threads

Dependency-prediction of instructions

Optimizing grouping of instructions

Optimizing grouping of instructions

Dynamic issue masks for processor hang prevention

Instruction and logic for scheduling instructions

Virtual machine coprocessor for accelerating software execution

Speculative register file read suppression

Register files for storing data operated on by instructions of multiple widths

Register files for storing data operated on by instructions of multiple widths

Apparatus and method of controlling power consumption of graphic processing unit (GPU) resources

LOW POWER INSTRUCTION BUFFER FOR HIGH PERFORMANCE PROCESSORS

Issuing instructions to multiple execution units

Method and system for generating object code to facilitate predictive memory retrieval

Determining if transactions that are about to run out of resources can be salvaged or need to be aborted

Systems and methods for processing both instructions and constant values from a memory of a digital processor accessed by separate pointers

Control of switching between executed mechanisms

Programmable power performance optimization for graphics cores

Resource sharing using process delay

Speculative finish of instruction execution in a processor core

Multi-user processor system for processing information

Branch prediction with power usage prediction and control

Implementing out of order processor instruction issue queue

Implementing out of order processor instruction issue queue

Automated decomposition for mixed integer linear programs with embedded networks requiring minimal syntax

Computer processor employing instructions with elided nop operations

Computer processor employing split-stream encoding

Restoring a register renaming map

Processing of multiple instruction streams in a parallel slice processor

Parallel slice processor with dynamic instruction stream mapping

Processing of multiple instruction streams in a parallel slice processor

Parallel slice processor with dynamic instruction stream mapping

Kick-started run-to-completion processing method that does not involve an instruction counter

Stunt box to broadcast and store results until retirement for an out-of-order processor

Method and system for determining instruction conflict states for issuance of memory instructions in a VLIW processor

Computer processor with generation renaming

Allocating resources to threads based on speculation metric

Select logic for the instruction scheduler of a multi strand out-of-order processor based on delayed reconstructed program order

Reuse of results of back-to-back micro-operations

Preventing duplicate execution by sharing a result between different processing lanes assigned micro-operations that generate the same result

Techniques for implementing barriers to efficiently support cumulativity in a weakly-ordered memory system

Techniques for implementing barriers to efficiently support cumulativity in a weakly-ordered memory system

Processor subroutine cache

Address re-ordering mechanism for efficient pre-fetch training in an out-of-order processor

Instruction and logic for reducing data cache evictions in an out-of-order processor

Instruction and logic for a memory ordering buffer

Chained-instruction dispatcher

VLIW processor including a state register for inter-slot data transfer and extended bits operations

Run time incremental compilation of script code

COMMITTING HARDWARE TRANSACTIONS THAT ARE ABOUT TO RUN OUT OF RESOURCE

Method and dynamically reconfigurable processor adapted for management of persistence of information across multiple instruction cycles

Completion time prediction for vector instructions

Completion time determination for vector instructions

Memory controller with transaction-queue-dependent power modes

Multithreading using an ordered list of hardware contexts

Vector mask driven clock gating for power efficiency of a processor

Method and apparatus for enabling a processor to generate pipeline control signals

System and processor for implementing interruptible batches of instructions

METHOD IN A PROCESSOR, AN APPARATUS AND A COMPUTER PROGRAM PRODUCT

Combined branch target and predicate prediction

Packet parsing engine

Techniques for hybrid computer thread creation and management

Arithmetic logical unit array, microprocessor, and method for driving an arithmetic logical unit array

CPU archtecture with highly flexible allocation of execution resources to threads

Accelerated code optimizer for a multiengine microprocessor

Instruction and logic for non-blocking register reclamation

Bypassing a store-conditional request around a store queue

Bypassing a store-conditional request around a store queue

Allocation of load instruction(s) to a queue buffer in a processor system based on prediction of an instruction pipeline hazard

Power gating functional units of a processor

Recording performance metrics to predict future execution of large instruction sequences on either high or low performance execution circuitry

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT TO ENABLE THE YIELDING OF THREADS IN A GRAPHICS PROCESSING UNIT TO TRANSFER CONTROL TO A HOST PROCESSOR

SIMD variable shift and rotate using control manipulation

Virtual load store queue having a dynamic dispatch window with a distributed structure

Energy efficient multi-modal instruction issue

Dispatching a stored instruction in response to determining that a received instruction is of a same instruction type

Prioritizing instructions based on type

Dynamically detecting uniformity and eliminating redundant computations to reduce power consumption

PIPELINED FINITE STATE MACHINE

Virtual load store queue having a dynamic dispatch window with a unified structure

System, method, and computer program product for implementing multi-cycle register file bypass

Technique for reducing voltage droop by throttling instruction issue rate

Predictive fetching and decoding for selected instructions

Early issue of null-predicated operations

Transactional memory that supports a get from one of a set of rings command

Split-word memory

Method and system for instruction scheduling

Memory controller with transaction-queue-monitoring power mode circuitry

System and method for an asynchronous processor with token-based very long instruction word architecture

System and method for an asynchronous processor with heterogeneous processors

System and method for an asynchronous processor with pepelined arithmetic and logic unit

Specialized memory disambiguation mechanisms for different memory read access types

INPUT DATA AGGREGATION PROCESSING APPARATUS, SYSTEM AND METHOD

Verifying forwarding paths in pipelines

Handling Operating System (Os) Transitions In An Unbounded Transactional Memory (Utm) Mode

Execution-aware memory protection

Dependent instruction suppression in a load-operation instruction

Dependent instruction suppression

System, method, and computer program product for managing out-of-order execution of program instructions

Hybrid tag scheduler to broadcast scheduler entry tags for picked instructions

Dynamic accessing of execution elements through modification of issue rules

Compact linked-list-based multi-threaded instruction graduation buffer

System for providing trace data in a data processor having a pipelined architecture

Method and apparatus for implementing dynamic portbinding within a reservation station

Multifunctional hexadecimal instruction form system and program product

Predictive fetching and decoding for selected instructions

Instruction order enforcement pairs of instructions, processors, methods, and systems

Method and apparatus for continued retirement during commit of a speculative region of code

Dependent instruction suppression

Dependence-based replay suppression

Systems and methods for managing reconfigurable processor cores

Method and apparatus for efficient scheduling for asymmetrical execution units

Processor with inter-execution unit instruction issue

Accelerated reversal of speculative state changes and resource recovery

Planning execution of tasks with dependency resolution

Increasing macroscalar instruction level parallelism

Techniques for scheduling operations at an instruction pipeline

Microprocessor that fuses if-then instructions

Pointer chasing prediction

Hierarchical hash tables for SIMT processing and a method of establishing hierarchical hash tables

Polymorphic heterogeneous multi-core architecture

Single cycle instruction pipeline scheduling

Mechanism for saving and retrieving micro-architecture context

Method for performing dual dispatch of blocks and half blocks

Signal processing device and signal processing method

Method for dependency broadcasting through a block organized source view data structure

Method for executing multithreaded instructions grouped into blocks

Method and apparatus to avoid deadlock during instruction scheduling using dynamic port remapping

Processor scheduling with thread performance estimation on cores of different types

Method for emulating a guest centralized flag architecture by using a native distributed flag architecture

Paralleizing loops in the presence of possible memory aliases

Efficient way to cancel speculative ‘source ready’ in scheduler for direct and nested dependent instructions

Method for populating register view data structure by using register template snapshots

Method for implementing a reduced size register view data structure in a microprocessor

Method for populating a source view data structure by using register template snapshots

Method for implementing a reduced size register view data structure in a microprocessor

Method for populating and instruction view data structure by using register template snapshots

Method for dependency broadcasting through a source organized source view data structure

Method and apparatus for nearest potential store tagging

Processor with hybrid pipeline capable of operating in out-of-order and in-order modes

Fusible instructions and logic to provide OR-test and AND-test functionality using multiple test sources

Execution context swap between heterogeneous functional hardware units

Apparatus and method for non-blocking execution of static scheduled processor

Parallel execution of instructions in processing units and adjusting power mode based on monitored data dependency over a period of time

Methods and apparatus for achieving thermal management using processing task scheduling

Parallel processing computer systems with reduced power consumption and methods for providing the same

Branch prediction with power usage prediction and control

Local instruction loop buffer utilizing execution unit register file

Extensible execution unit interface architecture with multiple decode logic and multiple execution units

Local instruction loop buffer utilizing execution unit register file

Extensible execution unit interface architecture with multiple decode logic and multiple execution units

Load latency speculation in an out-of-order computer processor

Load latency speculation in an out-of-order computer processor

Allocating resources to threads based on speculation metric

Completing load and store instructions in a weakly-ordered memory model

Data processing apparatus and method for controlling use of an issue queue to represent an instruction suitable for execution by a wide operand execution unit

Multi-level dispatch for a superscalar processor

Dynamic accessing of execution elements through modification of issue rules

Gather-op instruction to duplicate a mask and perform an operation on vector elements gathered via tracked offset-based gathering

Tracking speculative execution of instructions for a register renaming data store

Opportunistic utilization of redundant ALU

Apparatus and method for a hybrid latency-throughput processor

Vector address conflict resolution with vector population count functionality

Reducing energy and increasing speed by an instruction substituting subsequent instructions with specific function instruction

Performing frequency coordination in a multiprocessor system based on response timing optimization

Concurrent multiple instruction issue of non-pipelined instructions using non-pipelined operation resources in another processing core

Reconfigurable processor for parallel processing and operation method of the reconfigurable processor

Speculative finish of instruction execution in a processor core

Multiprocessor system

Providing hints to an execution unit to prepare for predicted subsequent arithmetic operations

LOAD/STORE PICKER

Multi-thread processor with rescheduling when threads are nondispatchable

Computer instructions for activating and deactivating operands