199657 ⎘
Erasable programmable read-only memories electrically programmable; Auxiliary circuits, e.g. for writing into memory; Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention; Arrangements for verifying correct programming or erasure; Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing Circuits or methods to prevent overprogramming of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
MEMORY SYSTEM
#2METHOD FOR PROGRAMMING A MEMORY SYSTEM
#3WEAR LEVELING IN SOLID STATE DRIVES
#4SIMULTANEOUS LOWER TAIL VERIFY WITH UPPER TAIL VERIFY
#5MEMORY SYSTEM
#6METHOD FOR PROGRAMMING A MEMORY SYSTEM
#7WEAR LEVELING IN SOLID STATE DRIVES
#8STORAGE DEVICE AND OPERATING METHOD THEREOF
#9Read level tracking and optimization
#10Read threshold optimization systems and methods by multi-dimensional search
#11Method for programming memory device to reduce retention error
#12Programming of memory devices
#13Non-volatile memory with countermeasure for over programming
#14Method for programming a memory system
#15Read level tracking and optimization
#16Method for programming a memory system
#17Programming of memory devices in response to programming voltages indicative of programming efficiency
#18Read level tracking and optimization
#19Wear leveling in solid state drives
#20Read level tracking and optimization
#21Programming of memory devices responsive to a stored representation of a programming voltage indicative of a programming efficiency
#22Memory system including semiconductor memory device and program method thereof
#23Immediate feedback before or during programming
#24EVENT TRIGGERED ERASURE FOR DATA SECURITY
#25Semiconductor memory device and operating method thereof
#26Programming of memory devices
#27Adaptive initial program voltage for non-volatile memory
#28Non-volatile memory with linear hot-electron injection technique and strain gauge using the same
#29Non-volatile memory system and method of programming the same
#30Limiting flash memory over programming
#31Non-volatile memory program algorithm device and method
#32Adaptive initial program voltage for non-volatile memory
#33System and method for adaptive bit rate programming of a memory device
#34Programming non-volatile memory with variable initial programming pulse
#35PFET nonvolatile memory
#36Driving method of semiconductor device
#37Programming non-volatile memory with high resolution variable initial programming pulse
#38Nonvolatile memory cell with well extending under transistor and data storage capacitor of memory cell
#39Programming non-volatile memory with bit line voltage step up
#40Flash memory device and system including the same
#41Programming non-volatile memory with high resolution variable initial programming pulse
#42Non-volatile semiconductor memory device capable of preventing over-programming
#43Non-volatile multilevel memory cell programming
#44Systems and methods for handling immediate data errors in flash memory
#45Programming non-volatile memory with high resolution variable initial programming pulse
#46Programming non-volatile memory with variable initial programming pulse
#47Semiconductor device and method of fabricating the same
#48Sector configure registers for a flash device generating multiple virtual ground decoding schemes
#49Flash mirror bit architecture using single program and erase entity as logical cell
#50Dynamic erase state in flash device
#51EEPROM emulation in flash device
#52Flash memory device and system including the same
#53Method for performing operations by applying periodic voltage pulses to control gate of an ono memory cell
#54Method of programming nonvolatile memory device
#55Memory cell and method of programming the same
#56Non-volatile multilevel memory cell programming
#57Hybrid non-volatile memory
#58Method of programming memory cell
#59pFET nonvolatile memory
#60Non-volatile memory device and erasing method thereof
#61Array source line (AVSS) controlled high voltage regulation for programming flash or EE array
#62Phase change memory device and related programming method
#63Semiconductor memory device
#64Counteracting overtunneling in nonvolatile memory cells
#65Array source line (AVSS) controlled high voltage regulation for programming flash or EE array
#66Method and apparatus for reference cell adjusting in a storage device
#67Faster programming of higher level states in multi-level cell flash memory
#68High speed programming system with reduced over programming
#69Hybrid non-volatile memory
#70Method and system for programming and inhibiting multi-level, non-volatile memory cells
#71Nonvolatile memory device capable of preventing over-erasure via modified tunneling through a double oxide layer between a floating gate and a control gate
#72Electronic memory, such as flash EPROM, with bitwise-adjusted writing current or/and voltage