199886 ⎘
Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor; Indexing scheme relating to and sub-groups for features not covered by these groups Multilevel memory cell aspects
Sub-classes:Semiconductor storage device and method of manufacturing semiconductor storage device
#2Interleaved two-pass data programming techniques with reduced write amplification
#3Double interleaved programming of a memory device in a memory sub-system
#4Systems for adaptively determining read threshold voltage using meta information
#5Memory management device, system and method
#6Two-layer code with low parity cost for memory sub-systems
#7Devices having a transistor and a capacitor along a common horizontal level, and methods of forming devices
#8Memory management device, system and method
#9Two-layer code with low parity cost for memory sub-systems
#10Devices having a transistor and a capacitor along a common horizontal level, and methods of forming devices
#11Memory system, reading method, program, and memory controller
#12Devices having a transistor and a capacitor along a common horizontal level, and methods of forming devices
#13Program verification time reduction in non-volatile memory devices
#14Programming memory cells using encoded TLC-fine