Semiconductor integrated circuit having write controlling circuit

Method for detecting erroneous word lines of a memory array and device thereof

SYSTEM AND METHOD FOR CHECKING ELECTRICAL CONTACT POINTS OF SEMICONDUCTOR DEVICES

Apparatus for testing memory device

Fuse monitoring circuit for semiconductor memory device

Fuse monitoring circuit for semiconductor memory device

Data output buffer circuit and semiconductor memory device including the same

Semiconductor memory device having a skew signal generator for adjusting a delay interval of internal circuitry

Test apparatus for determining if adjacent contacts are short-circuited and semiconductor integrated circuit devices that include such test apparatus

Semiconductor memory devices that are configured to analyze read failures and related methods of operating such devices

Fault injection in dynamic random access memory modules for performing built-in self-tests

POWER SUPPLY TESTING ARCHITECTURE

Integrated circuit including calibration circuit

Optimized phase change write method

Integrated circuit for setting a memory cell based on a reset current distribution

System and method for indicating status of an on-chip power supply system

SEMICONDUCTOR DEVICE AND TESTING METHOD THEREOF

Fuse apparatus for controlling built-in self stress and control method thereof

Scan sensing method that improves sensing margins

Method for reading nonvolatile memory at power-on stage

Nonvolatile semiconductor memory device

Magnetic random access memory and operating method of the same

Separate testing of continuity between an internal terminal in each chip and an external terminal in a stacked semiconductor device

SEMICONDUCTOR DEVICES AND METHOD OF TESTING SAME

Test circuit capable of sequentially performing boundary scan test and test method thereof

Semiconductor device

Techniques for configuring memory systems using accurate operating parameters

Output circuit for semiconductor device, semiconductor device having output circuit, and method of adjusting characteristics of output circuit

Circuit for controlling driver of semiconductor memory apparatus and method of controlling the same

Data channel test apparatus and method thereof

Method and apparatus for signaling between devices of a memory system

Apparatus, memory device and method of improving redundancy

NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH DUMMY CELLS AND METHOD OF PROGRAMMING THE SAME

Semiconductor memory device and driving method thereof

Electrical fuse self test and repair

Semiconductor memory device having data clock training circuit

Apparatus and method for detection of address decoder open faults

Semiconductor memory device capable of suppressing a coupling effect of a test-disable transmission line

Storage array including a local clock buffer with programmable timing

Semiconductor memory device

Delay locked loop circuit of semiconductor device

Multiple reference phase locked loop

Semiconductor integrated circuit and electronic device

Memory cell programming

Test method and semiconductor device

Magnetic random access memory and operation method thereof

Circuit architecture for radiation resilience

Integrated circuit memory having dynamically adjustable read margin and method therefor

Device Threshold Calibration Through State Dependent Burnin

Method and system for testing address lines

Semiconductor memory device

Reconfigurable connections for stacked semiconductor devices

High speed multiple memory interface I/O cell

Circuit for testing internal voltage of semiconductor memory apparatus

Compensation of non-volatile memory chip non-idealities by program pulse adjustment

Apparatus and method for implementing precise sensing of PCRAM devices

Deliberate destruction of integrated circuits

Memory control circuit and semiconductor device

Nonvolatile semiconductor memory

System, apparatus, and method to increase read and write stability of scaled SRAM memory cells

Memory device for detecting bit line leakage current and method thereof

On die thermal sensor of semiconductor memory device and method thereof

Delay stage-interweaved analog DLL/PLL

Digital calibration circuits, devices and systems including same, and methods of operation

Semiconductor integrated circuit

Apparatus and method for detecting word line leakage in memory devices

Memory module with termination component

Semiconductor memory device

SEMICONDUCTOR MEMORY DEVICE HAVING ANTIFUSE CIRCUITRY

Efficient clocking scheme for ultra high-speed systems

Semiconductor memory device changing refresh interval depending on temperature

Threshold voltage digitizer for array of programmable threshold transistors

Semiconductor memory device having memory block configuration

Error correction code (ECC) circuit test mode

Programmable diagnostic memory module

Efficient and systematic measurement flow on drain voltage for different trimming in flash silicon characterization

SEMICONDUCTOR INTEGRATED CIRCUIT

Word line driving circuit and method of testing a word line using the word line driving circuit

Multi-column decoder stress test circuit

Memory device trims

INTEGRATED CIRCUIT INCLUDING DECOUPLING CAPACITORS THAT CAN BE DISABLED

Semiconductor memory device changing refresh interval depending on temperature

Semiconductor memory, test method of semiconductor memory and system

Semiconductor memory capable of testing a failure before programming a fuse circuit and method thereof

Detection of address decoder faults

Semiconductor memory device

Circuits to delay a signal from a memory device

Voltage trimming

Monitoring VRM-induced memory errors

Method of testing data paths in an electronic circuit

SAMPLING CIRCUIT AND METHOD

Internal voltage generator and control method thereof, and semiconductor memory device and system including the same

Method and apparatus for repeatable drive strength assessments of high speed memory DIMMs

Method and apparatus for improving data transfer

Dynamic voltage adjustment for memory

Oscillation device, method of oscillation, and memory device

Semiconductor memory device

Semiconductor memory device

Semiconductor memory device and test method thereof

Memory system and semiconductor integrated circuit

Calibration circuit, semiconductor device including the same, and memory module

Local skew detecting circuit for semiconductor memory apparatus

Calibration system for writing and reading multiple states into phase change memory

Hybrid DRAM

Calibration system and method

Sense amplifier method and arrangement

Method for testing semiconductor memory device

Memory test mode for charge retention testing

Memory device bit line sensing system and method that compensates for bit line resistance variations

Program method with locally optimized write parameters

System and method for conditioning differential clock signals and integrated circuit load board using same

Method for improving stability and lock time for synchronous circuits

Semiconductor device including fuse and method for testing the same capable of suppressing erroneous determination

Method and apparatus for controlling reading level of memory cell

Method, Device And Computer Program For Evaluating A Signal Transmission

Redundancy memory cell access circuit and semiconductor memory device including the same

Apparatus for measuring on-die termination (ODT) resistance and semiconductor memory device having the same

Systems and devices including memory with built-in self test and methods of making and using the same

Memory refresh system and method

Digital filters for semiconductor devices

Digital filters with memory

Programming rate identification and control in a solid state memory

Fuse farm redundancy method and system

Word line driving circuit, semiconductor memory device including the same, and method for testing the semiconductor memory device

Semiconductor memory device with ZQ calibration

Semiconductor integrated circuit and method of allocating codes

Method and apparatus for controlling memory

Register with process, supply voltage and temperature variation independent propagation delay path

Integrated circuit memory device responsive to word line/bit line short-circuit

Semiconductor memory device and test method therefor

Antifuse replacement determination circuit and method of semiconductor memory device

Semiconductor device

Adjustable drive strength apparatus, systems, and methods

Memory device

Semiconductor device

Semiconductor device that uses a plurality of source voltages

Reducing effects of program disturb in a memory device

NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE MATERIALS

Stacked semiconductor device and method of testing the same

Method and circuit for stressing upper level interconnects in semiconductor devices

Measuring threshold voltage distribution in memory using an aggregate characteristic

Semiconductor device with self refresh test mode

Software-Controlled Dynamic DDR Calibration

Circuit and method to find wordline-bitline shorts in a DRAM

Semiconductor integrated circuit device

Storage cell design evaluation circuit including a wordline timing and cell access detection circuit

DIFFERENCE SIGNAL PATH TEST AND CHARACTERIZATION CIRCUIT

DRAM with hybrid sense amplifier

DRAM with word line compensation

DRAM STORAGE CAPACITOR WITHOUT A FIXED VOLTAGE REFERENCE

Semiconductor memory device having output impedance adjustment circuit and test method of output impedance

Semiconductor memory device capable of optimizing signal transmission power and power initializing method thereof

Method and apparatus for measuring device mismatches

Method and apparatus for testing the functionality of a page decoder

Apparatus and method for calibrating on-die termination in semiconductor memory device

Semiconductor integrated circuit

Method for decoding data in non-volatile storage using reliability metrics based on multiple reads

Semiconductor memory device and control method thereof

Methods and apparatus for testing delay locked loops and clock skew

Semiconductor memory device

Implementing calibration of DQS sampling during synchronous DRAM reads

Implementing calibration of DQS sampling during synchronous DRAM reads

Method and apparatus providing final test and trimming for a power supply controller

Systems, modules, chips, circuits and methods with delay trim value updates on power-up

Methods of testing fuse elements for memory devices

Method and circuit for stressing upper level interconnects in semiconductor devices

METHOD FOR TESTING A WORD LINE FAILURE

Method for checking the integrity of a clock tree

Semiconductor memory device and control signal generating method thereof

Device and method for compensating for voltage drops

Memory device with reduced standby power consumption and method for operating same

Semiconductor memory apparatus with write training function

Clock test apparatus and method for semiconductor integrated circuit

Self-refresh control circuit for detecting current flowing from current generator and semiconductor device including same

System and method for controlling timing of output signals

SEMICONDUCTOR INTEGRATED CIRCUIT

Over temperature detection apparatus and method thereof

DDR-SDRAM INTERFACE CIRCUITRY, AND METHOD AND SYSTEM FOR TESTING THE INTERFACE CIRCUITRY

Stacked semiconductor chip package with shared DLL signal and method for fabricating stacked semiconductor chip package with shared DLL signal

TEST SYSTEM AND HIGH VOLTAGE MEASUREMENT METHOD

Programmable voltage divider

Programmable SRAM source bias scheme for use with switchable SRAM power supply sets of voltages

Semiconductor device including adjustable driver output impedances

Asynchronous data transmission

Semiconductor device which transmits or receives a signal to or from an external memory by a DDR system

Method, system and circuit for operating a non-volatile memory array

On-chip self test circuit and self test method for signal distortion

Systems and methods for defect testing of externally accessible integrated circuit interconnects

Test scheme for fuse circuit

Circuit and method of testing a fail in a memory device

Method for testing internal high voltage in nonvolatile semiconductor memory device and related voltage output circuit

Semiconductor memory having function to determine semiconductor low current

Implementing Efuse sense amplifier testing without blowing the Efuse

Performance control of an integrated circuit

I/O interface circuit of intergrated circuit

Write latency tracking using a delay lock loop in a synchronous DRAM

Circuit for testing word line of semiconductor memory device

Sense amplifier screen circuit and screen method thereof

Method for decreasing program disturb in memory cells

Method of decreasing program disturb in memory cells

Delayed sense amplifier multiplexer isolation

System and method for compensating for PVT variation effects on the delay line of a clock signal

Redundancy circuit and semiconductor memory device

Asynchronous, high-bandwidth memory component using calibrated timing elements

Erasing flash memory using adaptive drain and/or gate bias

Flash memory device with shunt

Apparatus and method for adjusting slew rate in semiconductor memory device

Memory with word-line driver circuit having leakage prevention transistor

Method for evaluating storage cell design using a wordline timing and cell access detection circuit

Methods and apparatuses for trimming reference cells in semiconductor memory devices

Program time adjustment as function of program voltage for improved programming speed in memory system

DRAM architecture

DRAM with reduced power consumption

Data amplifying circuit for semiconductor integrated circuit

Data training system and method thereof

RAM with trim capacitors

DRAM WITH METAL-LAYER CAPACITORS

Semiconductor integrated circuit which properly executes an operational test of a circuit under test in the semiconductor integrated circuit

Circuits to delay a signal from DDR-SDRAM memory device including an automatic phase error correction

Method of output slew rate control

Output slew rate control

Calibration circuit

Flash memory device and method of testing a flash memory device

Semiconductor memory device having the operating voltage of the memory cell controlled

Nonvolatile semiconductor memory

Systems and methods for maintaining performance at a reduced power

TRAINING OF SIGNAL TRANSFER CHANNELS BETWEEN MEMORY CONTROLLER AND MEMORY DEVICE

Refresh period adjustment technique for dynamic random access memories (DRAM) and integrated circuit devices incorporating embedded DRAM

Digital calibration circuits, devices and systems including same, and methods of operation

Control signal training

System having a controller device, a buffer device and a plurality of memory devices

System for elevator electronic safety device

Method for automatic adjustment of timing of double data rate interface

Phase controlled high speed interfaces

Method of providing optimal field programming of electronic fuses

Memory device with configurable delay tracking

Memory access strobe configuration system and process

Apparatus and method for determining on die termination modes in memory device

Method of timing calibration using slower data rate pattern

Controlled reliability in an integrated circuit

Voltage monitoring device in semiconductor memory device

CIRCUITRY FOR RELIABILITY TESTING AS A FUNCTION OF SLEW

Offset compensated sensing for magnetic random access memory

Semiconductor memory device for adjusting impedance of data output driver

Memory, integrated circuit and methods for adjusting a sense amp enable signal used therewith

Semiconductor device

Memory cell supply voltage control based on error detection

Test circuit for testing command signal at package level in semiconductor device

Minimum memory operating voltage technique

Semiconductor memory device, memory system having semiconductor memory device, and method for testing memory system

SEMICONDUCTOR MEMORY AND METHOD FOR TESTING SEMICONDUCTOR MEMORIES

Phase shift adjusting method and circuit

Semiconductor memory device and method of controlling timing

Detection of row-to-row shorts and other row decode defects in memory devices

BALANCED SENSE AMPLIFIER CIRCUITS

Phase-change random access memory (PRAM) performing program loop operation and method of programming the same

Semiconductor device, method for measuring characteristics of element to be measured, and characteristic management system of semiconductor device

Circuit and method for selecting test self-refresh period of semiconductor memory device

Method of detecting bit line bridge by selectively floating even-or odd-numbered bit lines of memory device

Non-volatile memory with linear estimation of initial programming voltage

Method for non-volatile memory with reduced erase/write cycling during trimming of initial programming voltage

METHOD OF FIXING A READ EVALUATION TIME OR THE DIFFERENCE BETWEEN A READ CHARGE VOLTAGE AND A READ DISCRIMINATING VOLTAGE IN A NON-VOLATILE NAND TYPE MEMORY DEVICE

Method for non-volatile memory with linear estimation of initial programming voltage

Repair circuitry with an enhanced ESD protection device

Semiconductor memory device

Method for powering an electronic device and circuit

Memory device having function of detecting bit line sense amp mismatch

Test method for semiconductor memory device and semiconductor memory device therefor

Semiconductor device

Memory test system including semiconductor memory device suitable for testing an on-die termination, and method thereof

Semiconductor memory device and semiconductor device comprising the same

Line defect detection circuit for detecting weak line

Semiconductor integrated circuit and test method thereof

Handling of the transmit enable signal in a dynamic random access memory controller

Semiconductor nonvolatile memory trimming technique for output characteristic control and redundancy repair

Method and apparatus for reducing oscillation in synchronous circuits

Input and output circuit

Reuse of functional data buffers for pattern buffers in XDR DRAM

Method for adjusting programming/erasing time in memory system

Self-timing circuit with programmable delay and programmable accelerator circuits

On-chip EE-PROM programming waveform generation

Buffered memory having a control bus and dedicated data lines

Method and system for independent control of voltage and its temperature co-efficient in non-volatile memory devices

Semiconductor memory device capable of detecting bridge defects and bridge defect detecting method performed in the semiconductor memory device

System and method for simulating an aspect of a memory circuit

BALANCED SENSE AMPLIFIER CIRCUITS

Memory circuit using a reference for sensing

Semiconductor memory device

Active compensation for operating point drift in MRAM write operation

Data compression read mode for memory testing

Low cost high density rectifier matrix memory

Automatic regulation method for the reference sources in a non-volatile memory device and corresponding memory device

Reading phase change memories to reduce read disturbs

Low cost high density rectifier matrix memory

Apparatus and method for controlling a driver strength

Memory systems and memory modules

Circuit and method of controlling input/output sense amplifier of a semiconductor memory device

Semiconductor memory device and driving method thereof

Test circuit for semiconductor memory device

Semiconductor memory apparatus having plurality of sense amplifier arrays having different activation timing