199732 ⎘
Checking stores for correct operation ; Subsequent repair ; Testing stores during standby or offline operation Detection or location of defective auxiliary circuits, e.g. defective refresh counters
Sub-classes:MEMORY WITH BUILT-IN SYNCHRONOUS-WRITE-THROUGH REDUNDANCY AND ASSOCIATED TEST METHOD
#2APPARATUS AND METHOD FOR DIAGNOSING MEMORY
#3On-Die Termination of Address and Command Signals
#4MEMORY DEVICE WITH IMPROVED SENSING STRUCTURE
#5APPARATUSES AND METHODS FOR IDENTIFYING MEMORY DEVICES OF A SEMICONDUCTOR DEVICE SHARING AN EXTERNAL RESISTANCE
#6APPARATUSES AND METHODS FOR IDENTIFYING MEMORY DEVICES OF A SEMICONDUCTOR DEVICE SHARING AN EXTERNAL RESISTANCE
#7On-die termination of address and command signals
#8DYNAMIC PRIORITIZATION OF SELECTOR VT SCANS
#9TECHNIQUES TO COUPLE HIGH BANDWIDTH MEMORY DEVICE ON SILICON SUBSTRATE AND PACKAGE SUBSTRATE
#10SYSTEMS AND METHODS FOR TESTING ERROR CORRECTION CODE (ECC) LOGIC OF AUTOMOTIVE SAFETY SYSTEMS FOR FAULTS
#11MEMORY WITH BUILT-IN SYNCHRONOUS-WRITE-THROUGH REDUNDANCY AND ASSOCIATED TEST METHOD
#12ADAPTIVE INTERNAL ERROR SCRUBBING AND ERROR HANDLING
#13On-die termination of address and command signals
#14SYSTEMS AND METHODS TO DETECT CELL-INTERNAL DEFECTS
#15Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance
#16Techniques to couple high bandwidth memory device on silicon substrate and package substrate
#17Memory device with serial and parallel testing structure for sensing amplifiers
#18SYSTEMS AND METHODS FOR PLP CAPACITOR HEALTH CHECK
#19Dynamic prioritization of selector Vscans
#20Memory device for column repair
#21Techniques to couple high bandwidth memory device on silicon substrate and package substrate
#22On-die termination of address and command signals
#23METHODS AND APPARATUS FOR DYNAMICALLY ADJUSTING PERFORMANCE OF PARTITIONED MEMORY
#24Drift tracking feedback for communication channels
#25Systems and methods to detect cell-internal defects
#26Memory device with configurable performance and defectivity management
#27CONTROLLER AND METHOD OF OPERATING THE SAME
#28Memory device for column repair
#29Apparatuses and methods for refreshing memories with redundancy
#30Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance
#31Systems and methods to detect cell-internal defects
#32Techniques to couple high bandwidth memory device on silicon substrate and package substrate
#33Systems and methods for detecting and configuring lanes in a circuit system
#34Systems and methods for PLP capacitor health check
#35On-die termination of address and command signals
#36Apparatuses and methods for controlling word line discharge
#37Testing memory cells by allocating an access value to a memory access and granting an access credit
#38Methods and apparatus for dynamically adjusting performance of partitioned memory
#39Memory device with configurable performance and defectivity management
#40MEMORY CONTROLLER
#41Semiconductor memory device and method for refreshing memory with refresh counter
#42Glitch profiling in an integrated circuit
#43Apparatuses and methods for controlling word line discharge
#44Methods for programing DDR compatible open architecture resistive change element arrays
#45On-die termination of address and command signals
#46Systems and methods for identifying counterfeit memory
#47Memory controller and memory system having the same
#48Semiconductor devices
#49Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance
#50Drift tracking feedback for communication channels
#51On-die termination of address and command signals
#52Non-contact electron beam probing techniques and related structures
#53Resistive change element arrays using a reference line
#54Memory controller
#55Memory interface latch with integrated write-through and fence functions
#56Output impedance calibration for signaling
#57Memory devices configured to perform leak checks
#58Semiconductor memory device including a shift register
#59Techniques for providing signal calibration data
#60Semiconductor memory device and repair method thereof
#61Memory controller and memory system having the same
#62Memory device, memory address decoder, system, and related method for memory attack detection
#63Non-contact electron beam probing techniques and related structures
#64Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance
#65Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices
#66On-die termination of address and command signals
#67Semiconductor memory device and test method therefor
#68Apparatus and methods for through substrate via test
#69Testing memory cells by allocating an access value to a memory access and granting an access credit
#70System and method of inspecting substrate and method of fabricating semiconductor device using the same
#71Magnetic field generator
#72High performance memory controller
#73DRAM-level error injection and tracking
#74Memory device, memory system, and operating method of memory device
#75Technique for determining performance characteristics of electronic devices and systems
#76Method to dynamically inject errors in a repairable memory on silicon and a method to validate built-in-self-repair logic
#77Semiconductor memory device witih a built-in self test circuit for adjusting a memory device property
#78Non-volatile memory device having dummy cells and memory system including the same
#79Memory system and error correcting method of the same
#80Multi-dimensional optimization of electrical parameters for memory training
#81Semiconductor memory device and test method therefor
#82Resistive change element arrays with in situ initialization
#83Memory controller
#84Memory devices configured to perform leak checks
#85DDR compatible open array architectures for resistive change element arrays
#86Periodic ZQ calibration with traffic-based self-refresh in a multi-rank DDR system
#87Drift tracking feedback for communication channels
#88Digital filters with memory
#89Memory and logic lifetime simulation systems and methods
#90Technologies for estimating remaining life of integrated circuits using on-chip memory
#91On-chip diagnostic circuitry monitoring multiple cycles of signal samples
#92High performance memory controller
#93Memory device with internal measurement of functional parameters
#94Timed sense amplifier circuits and methods in a semiconductor memory
#95Electronic device having fault monitoring for a memory and associated methods
#96Semiconductor memory device and test method therefor
#97Method and system for analyzing a refresh rate of a volatile memory device
#98Semiconductor memory device
#99Memory controller
#100Methods for programming and accessing DDR compatible resistive change element arrays
#101Controller, semiconductor memory system and operating method thereof
#102Output circuit for semiconductor device, semiconductor device having output circuit, and method of adjusting characteristics of output circuit
#103Method and apparatus for evaluating and optimizing a signaling system
#104Semiconductor memory device, memory system including the same, and method of error correction of the same
#105Testing a feedback shift-register
#106On-die termination of address and command signals
#107High performance memory controller
#108Semiconductor devices and semiconductor systems including the same
#109Semiconductor device, test program, and test method
#110Semiconductor device and method for operating the same
#111Apparatus and methods for through substrate via test
#112Reading and writing to NAND flash memories using charge constrained codes
#113Semiconductor apparatus capable of preventing refresh error and memory system using the same
#114Memory controller
#115Program operations with embedded leak checks
#116Device and method for detecting controller signal errors in flash memory
#117Offset compensation for sense amplifiers
#118Address fault detection circuit
#119Detecting write disturb in multi-port memories
#120Methods and systems for die failure testing
#121Storage system data hardening
#122Automatic word line leakage measurement circuitry
#123Memory module set having offset memory module units facilitating pin connections to main IC, and semiconductor memory device and system including the same
#124Semiconductor device and method for operating the same
#125Semiconductor memory apparatus and training method using the same
#126Program operations with embedded leak checks
#127Error injection and error counting during memory scrubbing operations
#128On-board chip reader adapter (OCRA)
#129Semiconductor apparatus capable of preventing refresh error and memory system using the same
#130Error injection and error counting during memory scrubbing operations
#131Memory array test logic
#132Detecting write disturb in multi-port memories
#133Methods for calibrating a read data path for a memory interface
#134Drift tracking feedback for communication channels
#135Semiconductor memory device and semiconductor memory system including the same
#136Data storage device and operating method thereof
#137Output circuit for semiconductor device, semiconductor device having output circuit, and method of adjusting characteristics of output circuit
#138Digital filters with memory
#139Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock drift
#140Semiconductor devices and semiconductor systems including the same
#141Implementing ECC control for enhanced endurance and data retention of flash memories
#142Implementing ECC control for enhanced endurance and data retention of flash memories
#143Input buffer for semiconductor memory device and flash memory device including the same
#144Semiconductor devices and semiconductor systems including the same
#145On-die termination of address and command signals
#146Semiconductor memory device and method of wafer burn-in test for the same
#147System, method, and apparatus for improving the utility of storage media
#148Method and apparatus for evaluating and optimizing a signaling system
#149Read request processing apparatus
#150Method of refreshing volatile memory device
#151Memory module
#152Sense amplifier offset voltage reduction
#153Apparatus and methods for through substrate via test
#154Configuring storage cells
#155Memory system and method using stacked memory device dice, and system using the memory system
#156I/O circuit with phase mixer for slew rate control
#157Systems and methods for testing pages of data stored in a memory module
#158Methods and systems for reducing supply and termination noise
#159Semiconductor device and semiconductor system including the same
#160Bit based fuse repair
#161Select transistor tuning
#162Semiconductor integrated circuit with bist circuit
#163Output slew rate control
#164Semiconductor device performing stress test
#165Nonvolatile logic array with built-in test result signal
#166Drift tracking feedback for communication channels
#167Semiconductor device
#168Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock drift
#169Method and system for automated device testing
#170Select transistor tuning
#171Memory subsystem command bus stress testing
#172Memory subsystem data bus stress testing
#173Memory test with in-line error correction code logic
#174Application memory preservation for dynamic calibration of memory interfaces
#175Method of application memory preservation for dynamic calibration of memory interfaces
#176Computer memory test structure
#177On-die termination of address and command signals
#178Managing non-volatile media
#179Memory controller that enforces strobe-to-strobe timing offset
#180Method, system and apparatus for evaluation of input/output buffer circuitry
#181Memory interface circuits including calibration for CAS latency compensation in a plurality of byte lanes
#182Methods for operating a memory interface circuit including calibration for CAS latency compensation in a plurality of byte lanes
#183Adjusting bit-line discharge time in memory arrays based on characterized word-line delay and gate delay
#184Technique for determining performance characteristics of electronic devices and systems
#185System and method for providing voltage supply protection in a memory device
#186Semiconductor memory device, method of adjusting the same and information processing system including the same
#187Configuring storage cells
#188Memory device and memory system including the same
#189SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME
#190Dynamically calibrated DDR memory controller
#191Advanced converters for memory cell sensing and methods
#192Three-dimensional semiconductor memory device having compensating data skewing according to interlayer timing delay and method of de-skewing data therein
#193NAND flash memory employing bit line charge/discharge circuit
#194Semiconductor integrated circuit having array E-fuse and driving method thereof
#195Victim port-based design for test area overhead reduction in multiport latch-based memories
#196Providing reliability metrics for decoding data in non-volatile storage
#197Latency detection in a memory built-in self-test by using a ping signal
#198Semiconductor memory device changing refresh interval depending on temperature
#199Circuit for driving word line
#200Storage system data hardening
#201Method for detecting permanent faults of an address decoder of an electronic memory device
#202Offset compensation for sense amplifiers
#203Driver for DDR2/3 memory interfaces
#204Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock drift
#205Method of burn-in test of EEPROM or flash memories
#206SRAM cell writability
#207Method of screening static random access memories for pass transistor defects
#208High speed multiple memory interface I/O cell
#209Capacitance evaluation apparatuses and methods
#210Fully-buffered dual in-line memory module with fault correction
#211Memory cell supply voltage control based on error detection
#212I/O circuit with phase mixer for slew rate control
#213Methods for testing a memory embedded in an integrated circuit
#214Compensation of non-volatile memory chip non-idealities by program pulse adjustment
#215Multilevel DRAM
#216Advanced memory device having improved performance, reduced power and increased reliability
#217Semiconductor memory device with a skew signal generator for adjusting a delay interval of internal circuitry
#218Advanced memory device having improved performance, reduced power and increased reliability
#219Memory controller comprising adjustable transmitter impedance
#220Memory controller with selective data transmission delay
#221Providing test coverage of integrated ECC logic en embedded memory
#222Memory buffer for buffer-on-board applications
#223Memory buffer for buffer-on-board applications
#224Delay locked loop semiconductor apparatus that models a delay of an internal clock path
#225Semiconductor memory device and information processing apparatus including the same
#226DATA PROCESSING DEVICE AND METHOD OF READING TRIMMING DATA
#227Semiconductor memory device having memory block configuration
#228Setting a reference voltage in a memory controller trained to a memory device
#229TEST CIRCUIT, SEMICONDUCTOR MEMORY APPARATUS USING THE SAME, AND TEST METHOD OF THE SEMICONDUCTOR MEMORY APPARATUS
#230Output circuit for semiconductor device, semiconductor device having output circuit, and method of adjusting characteristics of output circuit
#231Memory controller
#232Memory interface with selectable evaluation modes
#233Semiconductor memory device for transferring data at high speed
#234Programming rate identification and control in a solid state memory
#235Apparatus, system, and method for managing solid-state storage media
#236Memory device with internal measurement of functional parameters
#237Advanced converters for memory cell sensing and methods
#238Methods and systems for reducing supply and termination noise
#239Threshold voltage digitizer for array of programmable threshold transistors
#240Method and apparatus for reducing oscillation in synchronous circuits
#241Output slew rate control
#242CIRCUIT AND METHOD FOR CORRECTING SKEW IN A PLURALITY OF COMMUNICATION CHANNELS FOR COMMUNICATING WITH A MEMORY DEVICE, MEMORY CONTROLLER, SYSTEM AND METHOD USING THE SAME, AND MEMORY TEST SYSTEM AND METHOD USING THE SAME
#243DELAY ADJUSTMENT DEVICE, SEMICONDUCTOR DEVICE AND DELAY ADJUSTMENT METHOD
#244Method and apparatus for evaluating and optimizing a signaling system
#245Semiconductor apparatus
#246Reconfigurable connections for stacked semiconductor devices
#247Semiconductor device performing stress test
#248Memory controller with emulative internal memory buffer
#249Apparatus for measuring data setup/hold time
#250Spin-transfer torque memory self-reference read method
#251Built-in self test for one-time-programmable memory
#252Offset compensation for sense amplifiers
#253Storage system logical block address de-allocation management
#254Technique for determining performance characteristics of electronic devices and systems
#255Control voltage tracking circuits, methods for recording a control voltage for a clock synchronization circuit and methods for setting a voltage controlled delay
#256Method for manufacturing a stacked device conductive path connectivity
#257Memory control circuit, memory control method, and integrated circuit
#258DRAM memory controller with built-in self test and methods for use therewith
#259Memory systems and memory modules
#260Asynchronous pipelined memory access
#261Memory devices having programmable elements with accurate operating parameters stored thereon
#262Word line driving circuit, semiconductor memory device including the same, and method for testing the semiconductor memory device
#263Semiconductor system and data training method thereof
#264Apparatus and method for testing one-time-programmable memory
#265Semiconductor device and test method thereof
#266Detection of word-line leakage in memory arrays: current based approach
#267Detection of broken word-lines in memory arrays
#268Detection of word-line leakage in memory arrays
#269Duty cycle correction circuit
#270Calibrating resistance for integrated circuit
#271Integrated circuit and method for controlling data output impedance
#272Semiconductor device capable of suppressing a coupling effect of a test-disable transmission line
#273Semiconductor device
#274Integrated circuit
#275Input buffer circuit capable of adjusting variation in skew
#276Voltage trimming
#277Method and Circuit for Configuring Memory Core Integrated Circuit Dies with Memory Interface Integrated Circuit Dies
#278Threshold voltage digitizer for array of programmable threshold transistors
#279Semiconductor device
#280Memory cell supply voltage control based on error detection
#281Setting a reference voltage in a memory controller trained to a memory device
#282TEST SYSTEM AND HIGH VOLTAGE MEASUREMENT METHOD
#283Output apparatus and test apparatus
#284Memory system and method using stacked memory device dice, and system using the memory system
#285Integrated circuit and semiconductor memory device
#286Semiconductor devices having a three-dimensional stacked structure and methods of de-skewing data therein
#287Memory device having a local current sink
#288Methods for defect testing of externally accessible integrated circuit interconnects
#289Semiconductor memory device and method for testing the same
#290Apparatus and methods for through substrate via test
#291Semiconductor device with anti-fuse elements
#292Semiconductor memory device having memory block configuration
#293Test device and semiconductor integrated circuit device
#294Dynamically calibrated DDR memory controller
#295Dynamic random access memory (DRAM) refresh
#296Nonvolatile semiconductor memory and method for testing the same
#297Method and circuit for calibrating data capture in a memory controller
#298Semiconductor device
#299Global line sharing circuit of semiconductor memory device
#300Method and apparatus for reducing oscillation in synchronous circuits