199734 ⎘
Checking stores for correct operation ; Subsequent repair ; Testing stores during standby or offline operation; Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
FUNNEL-LIKE SHAPE INPUT/OUTPUT REPAIR MECHANISM CAPABLE OF SIMPLIFYING TRACE ROUTING DESIGN
#2DYNAMIC SELECT GATE SCAN MANAGEMENT
#3INTERPOSERS FOR MEMORY DEVICE TESTING AND CHARACTERIZATION, INCLUDING INTERPOSERS FOR TESTING AND CHARACTERIZING DECISION FEEDBACK EQUALIZATION CIRCUITRY OF DDR5 MEMORY DEVICES
#4READ RETRY WITH PHYSICAL DEFECT JUDGEMENT
#5MANAGING FAILURES OF IN-MEMORY COMPUTER (IMC) DEVICES
#6DETECTING MEMORY READ ERRORS BY TRIGGERING MORE WORD LINE SCANS IF NEEDED
#7METHODS OF OPERATING MEMORY DEVICE AND RELATED APPARATUSES
#8APPARATUSES, SYSTEMS, AND METHODS FOR STORING MEMORY METADATA
#9APPARATUSES, SYSTEMS, AND METHODS FOR STORING MEMORY METADATA
#10SEMICONDUCTOR DEVICE, MEMORY SYSTEM AND INFORMATION PROCESSING SYSTEM
#11STORAGE DEVICE AND OPERATING METHOD OF THE SAME
#12MEMORY DEVICE INCLUDING DIGITAL TEMPERATURE SENSOR
#13OPERATING METHOD OF MEMORY APPARATUS, MEMORY SYSTEM, AND OPERATING METHOD OF MEMORY SYSTEM
#14CONTROLLER, STORAGE DEVICE AND METHOD FOR OPERATING STORAGE DEVICE
#15MEMORY DEVICES PERFORMING MEMORY ACCESS OPERATION AND REPAIR OPERATION
#16DETECTION AND RETIREMENT OF DEFECTIVE BLOCKS
#17SEMICONDUCTOR DEVICE PERFORMING TESTS AND TEST METHOD OF THE SEMICONDUCTOR DEVICE
#18ROW ERROR MONITORING FOR MEMORY SYSTEMS
#19REPAIR TECHNIQUES FOR COUPLED MEMORY DIES
#20MEMORY WITH DATA BUS (DQ) MAPPINGS BASED ON FAULT BOUNDARY REQUIREMENTS, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS
#21DEFECTIVE WORD LINE SCAN
#22MULTI-CHANNEL MEMORY STACK WITH SHARED DIE
#23PROBABILISTIC DATA INTEGRITY SCANS USING RISK FACTOR ESTIMATION
#24MEMORY DEVICE AND ERROR CORRECTION METHOD THEREOF
#25DEFECTIVE WORD LINE BASED READ SCAN
#26MEMORY DEVICES AND SYSTEMS WITH PARALLEL IMPEDANCE ADJUSTMENT CIRCUITRY AND METHODS FOR OPERATING THE SAME
#27MEMORY DEVICE FOR COUNTING SEQUENCE OF OPERATION
#28SUB-BLOCK PROTECTION FOR MEMORY DEVICES
#29DUMMY MEMORY HOLE DEFECT DETECTION
#30SEMICONDUCTOR DEVICE AND OPERATING METHOD USING THE SAME
#31DIE-ON-HOLD FLAG
#32Data Storage Device and Method for Read Disturb Mitigation During Low-Power Modes
#33COMPONENT DIE VALIDATION BUILT-IN SELF-TEST (VBIST) ENGINE
#34METHOD, DEVICE, AND APPARATUS WITH MEMORY REPAIR BASED ON EXCLUSIVE-OR
#35NON-VOLATILE MEMORY WITH ENHANCED EARLY PROGRAM TERMINATION MODE FOR NEIGHBOR PLANE DISTURB
#36On-Die Termination of Address and Command Signals
#37ENHANCED ERROR CORRECTION CODE FOR ERROR DETECTION AND CORRECTION IN MULTI-LEVEL CELL-BASED MEMORY DEVICES
#38FLASH MEMORY AND TESTING METHOD THEREOF
#39DETECTING EXTRINSIC BITLINE DEFECTS
#40MEMORY DEVICE, MEMORY SYSTEM, AND OPERATION METHOD OF MEMORY DEVICE
#41APPARATUSES AND METHODS FOR IDENTIFYING MEMORY DEVICES OF A SEMICONDUCTOR DEVICE SHARING AN EXTERNAL RESISTANCE
#42MEMORY DEVICE FOR SUPPORTING COMMAND BUS TRAINING MODE AND METHOD OF OPERATING THE SAME
#43MEMORY DEVICE, MEMORY SYSTEM, AND READ OPERATION METHOD THEREOF
#44APPARATUS AND METHOD FOR CHANGING A READ VOLTAGE APPLIED FOR READING DATA FROM A NON-VOLATILE MEMORY CELL
#45MEMORY DEVICE FOR SUPPORTING COMMAND BUS TRAINING MODE AND METHOD OF OPERATING THE SAME
#46APPARATUSES AND METHODS FOR GRANULAR SINGLE-PASS METADATA ACCESS OPERATIONS
#47BLOCK FAMILY ERROR AVOIDANCE BIN SCANS AFTER MEMORY DEVICE POWER-ON
#48APPARATUSES AND METHODS FOR IDENTIFYING MEMORY DEVICES OF A SEMICONDUCTOR DEVICE SHARING AN EXTERNAL RESISTANCE
#49LOW-POWER SOURCE-SYNCHRONOUS SIGNALING
#50INTEGRATED CIRCUIT AND METHOD OF OPERATING SAME
#51EFFICIENT SOFT DECODING OF ERROR CORRECTION CODE VIA EXTRINSIC BIT INFORMATION
#52On-die termination of address and command signals
#53EVOLVING BAD BLOCK DETECTION IN NON-VOLATILE MEMORY
#54MEMORY SYSTEM, METHOD OF OPERATING MEMORY SYSTEM, AND COMPUTER-READABLE STORAGE MEDIUM
#55BUFFER CIRCUIT WITH ADAPTIVE REPAIR CAPABILITY
#56METHOD OF ERROR CORRECTION CODE (ECC) DECODING AND MEMORY SYSTEM PERFORMING THE SAME
#57ERROR HANDLING DURING A MEMORY COMPACTION PROCESS
#58SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD OF THE SAME
#59DATA TRANSMISSION USING DELAYED TIMING SIGNALS
#60NONVOLATILE MEMORY INCLUDING ON-DIE-TERMINATION CIRCUIT AND STORAGE DEVICE INCLUDING THE NONVOLATILE MEMORY
#61MEMORY DEVICE AND READING METHOD THEREOF
#62MEMORY DEVICE AND READING METHOD THEREOF
#63AREA SAVING HIGH COVERAGE FAST DIAGNOSIS MEMORY SCAN DESIGN
#64MEMORY BLOCK PROGRAMMING USING DEFECTIVITY INFORMATION
#65FAILSAFE MEMORY CARD ARCHITECTURE USING VOLTAGE DRIVER OUTPUT ENABLE SIGNALS
#66SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING
#67ADAPTIVE BLOCK FAMILY ERROR AVOIDANCE SCAN BASED ON DYNAMIC PAGE ERROR STATISTICS
#68EFFICIENT READ DISTURB SCANNING
#69Efficient soft decoding of error correction code via extrinsic bit information
#70CONTINUOUS ADAPTIVE DATA CAPTURE OPTIMIZATION FOR INTERFACE CIRCUITS
#71Techniques for determining an interface connection status
#72DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD
#73PROTOCOL FOR MEMORY POWER-MODE CONTROL
#74PROTECTING MEMORY CONTROLS AND ADDRESS
#75STORAGE DEVICES HAVING ENHANCED ERROR DETECTION AND MEMORY CELL REPAIR
#76PAGE BUFFER BLOCK AND MEMORY DEVICE INCLUDING THE SAME
#77NON-VOLATILE MEMORY WITH SMART CONTROL OF OVERDRIVE VOLTAGE
#78PASS VOLTAGE ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE
#79REPAIR TECHNIQUES FOR COUPLED MEMORY DIES
#80PROGRAM VERIFY COMPENSATION BY SENSING TIME MODULATION IN A MEMORY DEVICE WITH A DEFECTIVE DECK
#81PROBABILISTIC DATA INTEGRITY SCANS USING RISK FACTOR ESTIMATION
#82Programmable memory timing
#83At-speed test of functional memory interface logic in devices
#84Double data rate (DDR) memory controller apparatus and method
#85On-die termination of address and command signals
#86Continuous adaptive data capture optimization for interface circuits
#87Memory device including error correction device
#88Built-in self-test circuitry
#89Buffer circuit with adaptive repair capability
#90MEMORY DEVICE INCLUDED IN MEMORY SYSTEM AND METHOD FOR DETECTING FAIL MEMORY CELL THEREOF
#91Block family error avoidance bin scans after memory device power-on
#92Data processing method, data processing structure and memory
#93COMPOSITE TESTING MACHINE AND METHOD FOR USING COMPOSITE TESTING MACHINE
#94Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance
#95Memory block programming using defectivity information
#96Dynamic random access memory built-in self-test power fail mitigation
#97Nonvolatile memory including on-die-termination circuit and storage device including the nonvolatile memory
#98Low-power source-synchronous signaling
#99OPERATING AND TESTING SEMICONDUCTOR DEVICES
#100Component die validation built-in self-test (VBIST) engine
#101Data storage device for checking a defect of row lines and an operation method thereof
#102INTERPOSERS FOR MEMORY DEVICE TESTING AND CHARACTERIZATION, INCLUDING INTERPOSERS FOR TESTING AND CHARACTERIZING DECISION FEEDBACK EQUALIZATION CIRCUITRY OF DDR5 MEMORY DEVICES
#103Data storage apparatus comprising cell section operable as dosimeter and method of operating
#104Integrated circuit and operation method and inspection method thereof
#105Memory and operation method of memory
#106MEMORY DEVICE, SYSTEM AND METHOD EMPLOYING MULTIPHASE CLOCK
#107Semiconductor memory device and method of reading a semiconductor memory device
#108System and method for receiver equalization and stressed eye testing methodology for DDR5 memory controller
#109Techniques for determining an interface connection status
#110Memory device for supporting command bus training mode and method of operating the same
#111Protocol for memory power-mode control
#112Mediating directed refresh management induced row hammer and row access strobe (RAS) clobber failures
#113Methods and apparatus for testing inaccessible interface circuits in a semiconductor device
#114ROW ACCESS STROBE (RAS) CLOBBER AND ROW HAMMER FAILURE MITIGATION
#115Row access strobe (RAS) clobber and row hammer failures using a deterministic protocol
#116COMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS
#117Method of error correction code (ECC) decoding and memory system performing the same
#118Memory device, memory system, and read operation method thereof
#119Buffer circuit with adaptive repair capability
#120Memory controller for a memory device
#121Voltage calibration scans to reduce memory device overhead
#122Semiconductor memory systems with on-die data buffering
#123Data transmission using delayed timing signals
#124Test method for tolerance against the hot carrier effect
#125Memory device, memory system, and operation method of memory device
#126Low power signaling interface
#127MEMORY DEVICES AND SYSTEMS WITH PARALLEL IMPEDANCE ADJUSTMENT CIRCUITRY AND METHODS FOR OPERATING THE SAME
#128On-die termination of address and command signals
#129Controller and semiconductor system including a controller
#130I/O buffer offset mitigation
#131Semiconductor device having interconnection in package and method for manufacturing the same
#132Semiconductor device and memory system
#133Memory device including redundancy mats
#134Semiconductor device
#135Drift tracking feedback for communication channels
#136Voltage calibration scans to reduce memory device overhead
#137Vehicle memory system based on 3D memory and method operating thereof
#138Memory controller with integrated test circuitry
#139Protocol for memory power-mode control
#140Double data rate (DDR) memory controller apparatus and method
#141Method for performing memory calibration, associated system on chip integrated circuit and non-transitory computer-readable medium
#142Continuous adaptive data capture optimization for interface circuits
#143Nonvolatile memory including on-die-termination circuit and storage device including the nonvolatile memory
#144Programmable memory timing
#145Storage devices and methods of operating storage devices
#146Configurable termination circuitry
#147Periodic calibrations during memory device self refresh
#148Low-power source-synchronous signaling
#149Memory device for supporting command bus training mode and method of operating the same
#150Communication channel calibration for drift conditions
#151Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance
#152Buffer circuit with adaptive repair capability
#153Impedance calibration via a number of calibration circuits, and associated methods, devices and systems
#154Area-efficient dynamic memory redundancy scheme with priority decoding
#155Semiconductor memory device
#156Memory controller device and phase calibration method
#157SERDES link training
#158AT-SPEED TEST OF FUNCTIONAL MEMORY INTERFACE LOGIC IN DEVICES
#159Memory device, memory system, and operation method of memory device
#160Impedance calibration via a number of calibration circuits, and associated methods, devices, and systems
#161Memory with per pin input/output termination and driver impedance calibration
#162Input/output circuit internal loopback
#163Memory device with improved sensing structure
#164Memory circuit
#165Controller and semiconductor system including a controller
#166On-die termination of address and command signals
#167Semiconductor device having interconnection in package and method for manufacturing the same
#168Continuous adaptive data capture optimization for interface circuits
#169Transmitting data and power to a memory sub-system for memory device testing
#170Configurable termination circuitry
#171Protocol for memory power-mode control
#172Nonvolatile memory including on-die-termination circuit and storage device including the nonvolatile memory
#173Semiconductor memory systems with on-die data buffering
#174Techniques to calibrate an impedance level
#175Semiconductor device and memory system
#176Plurality of edge through-silicon vias and related systems, methods, and devices
#177METHODS FOR MEMORY INTERFACE CALIBRATION
#178Semiconductor memory device
#179I/O buffer offset mitigation while applying a same voltage level to two inputs of an input buffer
#180Memory controller with integrated test circuitry
#181MEMORY CONTROLLER
#182Systems and methods for writing zeros to a memory array
#183Periodic calibrations during memory device self refresh
#184Data transmission using delayed timing signals
#185On-die termination of address and command signals
#186Communication channel calibration for drift conditions
#187System and method for receiver equalization and stressed eye testing methodology for DDR5 memory controller
#188Memory modules, memory systems and methods of operating memory modules
#189Double data rate (DDR) memory controller apparatus and method
#190Memory device and method for supporting command bus training mode based on one data signal
#191Protocol for memory power-mode control
#192Synchronous signaling interface with over-clocked timing reference
#193Controller and semiconductor system including a controller
#194Nonvolatile memory including on-die-termination circuit and storage device including the nonvolatile memory
#195Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance
#196Semiconductor memory device
#197Drift tracking feedback for communication channels
#198On-die termination of address and command signals
#199DYNAMIC RANDOM ACCESS MEMORY BUILT-IN SELF-TEST POWER FAIL MITIGATION
#200Memory devices and systems with parallel impedance adjustment circuitry and methods for operating the same
#201Electronic device performing training on memory device by rank unit and training method thereof
#202Semiconductor device having interconnection in package and method for manufacturing the same
#203Voltage reference computations for memory decision feedback equalizers
#204Semiconductor device having interconnection in package and method for manufacturing the same
#205Semiconductor device including buffer circuit
#206Low-power source-synchronous signaling
#207Semiconductor memory systems with on-die data buffering
#208Semiconductor device and memory system
#209Buffer circuit with adaptive repair capability
#210Double data rate (DDR) memory controller apparatus and method
#211Apparatus for low power write and read operations for resistive memory
#212Memory device and divided clock correction method thereof
#213Systems and methods for writing zeros to a memory array
#214Data output buffer having pull-up main driver and memory device having the data output buffer
#215Flexible DLL (delay locked loop) calibration
#216Semiconductor device having interconnection in package and method for manufacturing the same
#217Controller and semiconductor system including a controller
#218Voltage reference computations for memory decision feedback equalizers
#219Nonvolatile memory including on-die-termination circuit and storage device including the nonvolatile memory
#220Memory controller
#221Communication channel calibration for drift conditions
#222Semiconductor memory device
#223Output impedance calibration for signaling
#224Methods for memory interface calibration
#225DQS-offset and read-RTT-disable edge control
#226CONTINUOUS ADAPTIVE DATA CAPTURE OPTIMIZATION FOR INTERFACE CIRCUITS
#227Nonvolatile memory including on-die-termination circuit and storage device including the nonvolatile memory
#228Memory controller with integrated test circuitry
#229Semiconductor memory device
#230Method and apparatus of using parity to detect random faults in memory mapped configuration registers
#231Safety enhancement for memory controllers
#232I/O buffer offset mitigation
#233Double data rate (DDR) memory controller apparatus and method
#234Integrated circuit chip
#235Storage device including calibration device
#236Protocol for memory power-mode control
#237Memory system for adjusting clock frequency
#238Memory modules, memory systems and methods of operating memory modules
#239Systems and methods for writing zeros to a memory array
#240Enabling high at-speed test coverage of functional memory interface logic by selective usage of test paths
#241Memory device for supporting command bus training mode and method of operating the same
#242Protocol for memory power-mode control
#243Semiconductor device and system performing calibration operation
#244Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance
#245On-die termination of address and command signals
#246Identifying error types among flash memory
#247Electronic system generating multi-phase clocks and training method thereof
#248Data transmission and reception system, data transmission and reception device, and method of controlling data transmission and reception system
#249Apparatus and methods for through substrate via test
#250Semiconductor device and system performing calibration operation
#251DQS-offset and read-RTT-disable edge control
#252Dynamic reconfiguration and management of memory using field programmable gate arrays
#253Interface adjustment processes for a data storage device
#254Periodic calibrations during memory device self refresh
#255Platform debug and testing with secured hardware
#256Serdes link training
#257Methods and systems for averaging impedance calibration
#258Protocol for memory power-mode control
#259Impedance compensation based on detecting sensor data
#260Multi-channel nonvolatile memory power loss management
#261Low power signaling interface
#262Calibrating I/O impedances using estimation of memory die temperature
#263Apparatus for low power write and read operations for resistive memory
#264Nonvolatile memory including on-die-termination circuit and storage device including the nonvolatile memory
#265Double data rate (DDR) memory controller apparatus and method
#266Technique for determining performance characteristics of electronic devices and systems
#267Double data rate (DDR) memory controller apparatus and method
#268Memory store error check
#269Semiconductor memory device
#270Wiring with external terminal
#271Inspection circuit, semiconductor storage element, semiconductor device, and connection inspection method
#272DRAM having a plurality of registers
#273Embedded memory testing with storage borrowing
#274Input/output terminal characteristic calibration circuit and semiconductor apparatus including the same
#275Method of phase calibration for double data rate memory interface and related system
#276Systems and methods of adjusting an interface bus speed
#277Platform component interconnect testing
#278Methods for memory interface calibration
#279Data transmission using delayed timing signals
#280Wire order testing method and associated apparatus
#281Training controller, and semiconductor device and system including the same
#282Output buffer circuit and memory device including the same
#283High speed and high precision characterization of VTsat and VTlin of FET arrays
#284Memory device and divided clock correction method thereof
#285Semiconductor device and memory system
#286Semiconductor device and memory controller receiving differential signal
#287Semiconductor devices for impedance calibration including systems and methods thereof
#288Semiconductor memory device
#289Semiconductor device
#290Method for calibrating capturing read data in a read data path for a DDR memory interface circuit
#291Semiconductor device and semiconductor system
#292Electronics device performing software training on memory channel and memory channel training method thereof
#293Memory controller
#294Semiconductor device including buffer circuit
#295Correcting a data storage error caused by a broken conductor using bit inversion
#296Periodic ZQ calibration with traffic-based self-refresh in a multi-rank DDR system
#297Memory module, memory controller and associated control method for read training technique
#298Drift tracking feedback for communication channels
#299Shift register unit, gate line driving device, and driving method
#300Semiconductor device having interconnection in package and method for manufacturing the same