199734 ⎘
Checking stores for correct operation ; Subsequent repair ; Testing stores during standby or offline operation; Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
Nonvolatile memory device, memory system including the same and method of operating the same
#302Buffer circuit with adaptive repair capability
#303Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses
#304Data communication system and data receiving device
#305Memory system for rapidly testing data lane integrity
#306On-chip diagnostic circuitry monitoring multiple cycles of signal samples
#307Semiconductor apparatus with reduced risks of chip counterfeiting and network invasion
#308Flexible DLL (delay locked loop) calibration
#309Low-power source-synchronous signaling
#310Semiconductor device having impedance calibration function to data output buffer and semiconductor module having the same
#311Semiconductor device, adjustment method thereof and data processing system
#312Memory device and correction method
#313System and method of transferring data over available pins
#314On-chip aging sensor and counterfeit integrated circuit detection method
#315Diagnosis method for diagnosing memory, transmission apparatus, and computer-readable recording medium
#316Location-based optimization for memory systems
#317Memory module monitoring memory operation and power management method thereof
#318Method and apparatus for determining status element total with sequentially coupled counting status circuits
#319Semiconductor memory systems with on-die data buffering
#320Redundancy memory device comprising a plurality of selecting circuits
#321Continuous adaptive data capture optimization for interface circuits
#322Source-synchronous data transmission with non-uniform interface topology
#323Memory controller
#324Output buffer circuit with low sub-threshold leakage current
#325Three-dimensional flash memory system
#326Multiple gating modes and half-frequency dynamic calibration for DDR memory controllers
#327Memory interface system
#328Output circuit for semiconductor device, semiconductor device having output circuit, and method of adjusting characteristics of output circuit
#329Semiconductor memory device providing analysis and correcting of soft data fail in stacked chips
#330Method and apparatus for evaluating and optimizing a signaling system
#331Semiconductor storage device and control method thereof
#332Semiconductor system and method for testing semiconductor device
#333On-die termination of address and command signals
#334Semiconductor devices and semiconductor systems including the same
#335Apparatus and methods for through substrate via test
#336Integrated circuit and storage device including the same
#337Semiconductor devices and semiconductor systems including the same
#338Memory controller
#339Methods and apparatus for testing inaccessible interface circuits in a semiconductor device
#340Apparatus for low power write and read operations for resistive memory
#341Output buffer circuit with low sub-threshold leakage current
#342Semiconductor device having impedance calibration function to data output buffer and semiconductor module having the same
#343Semiconductor memory apparatus including an internal generation circuit configured to generate test data
#344Semiconductor apparatus and test device therefor
#345Multiple gating modes and half-frequency dynamic calibration for DDR memory controllers
#346AC stress mode to screen out word line to word line shorts
#347Semiconductor device having interconnection in package and method for manufacturing the same
#348Continuous adaptive data capture optimization for interface circuits
#349Semiconductor memory apparatus and training method using the same
#350Semiconductor device having output buffers and voltage path coupled to output buffers
#351Margin tool for double data rate memory systems
#352System including memories sharing calibration reference resistor and calibration method thereof
#353Electronic system generating multi-phase clocks and training method thereof
#354Source-synchronous data transmission with non-uniform interface topology
#355Distributed clock synchronization
#356SYSTEM AND METHOD OF INCREASING RELIABILITY OF NON-VOLATILE MEMORY STORAGE
#357Apparatus for measuring signal skew of asynchronous flash memory controller
#358Nonvolatile memory device and storage device having the same
#359Configurable delay circuit and method of clock buffering
#360Semiconductor memory apparatus converting serial type data into parallel type data in response to pipe control signals and pipe control signals during a training operation
#361Channel skewing
#362Low-pin-count non-volatile memory interface with soft programming capability
#363Method and apparatus for monitoring general purpose input output, GPIO, signals
#364Drift tracking feedback for communication channels
#365Nonvolatile memory device and method of operating the same
#366Output circuit for semiconductor device, semiconductor device having output circuit, and method of adjusting characteristics of output circuit
#367Semiconductor device, adjustment method thereof and data processing system
#368On chip characterization of timing parameters for memory ports
#369Method and apparatus for maintaining an accurate I/O calibration cell
#370Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock drift
#371Semiconductor memory device including output buffer
#372Memory interface
#373Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses
#374Semiconductor memory systems with on-die data buffering
#375Semiconductor system
#376Circuit for controlling write leveling of a target module and a method thereof
#377Digital calibration-based skew cancellation for long-reach MIPI D-PHY serial links
#378Integrated circuit comprising buffer chain
#379Data pattern generation for I/O testing of multilevel interfaces
#380Data pattern generation for I/O testing
#381Avoiding DQS false sampling triggers
#382Detecting defective connections in stacked memory devices
#383Detecting defective connections in stacked memory devices
#384On-die termination of address and command signals
#385Method for performing memory interface calibration in an electronic device, and associated apparatus and associated memory controller
#386Multi-cycle write leveling
#387Dynamic interface calibration for a data storage device
#388Semiconductor memory apparatus
#389IO driver impedance calibration
#390Memory controller, computing device with a memory controller, and method for calibrating data transfer of a memory system
#391Semiconductor apparatus and testing method thereof
#392Protocol for memory power-mode control
#393Method and apparatus for reference voltage calibration in a single-ended receiver
#394Impedance calibration circuits
#395Memory interface with integrated tester
#396Fast recalibration circuitry for input/output (IO) compensation finite state machine power-down-exit
#397Method and apparatus for evaluating and optimizing a signaling system
#398Semiconductor device
#399Semiconductor devices, semiconductor systems including the same, and methods of inputting data into the same
#400Method for testing semiconductor apparatus and test system using the same
#401Memory module
#402Semiconductor device having impedance calibration function to data output buffer and semiconductor module having the same
#403Output circuit and semiconductor storage device
#404Apparatus and methods for through substrate via test
#405Dynamic memory signal phase tracking method and associated control circuit
#406I/O driver transmit swing control
#407Memory access alignment in a double data rate (‘DDR’) system
#408Semiconductor circuit and leakage current test system
#409I/O circuit with phase mixer for slew rate control
#410Low-power source-synchronous signaling
#411Analysis support apparatus, analysis support method, and computer product
#412Data transmission using delayed timing signals
#413Semiconductor device including output circuit constituted of plural unit buffer circuits in which impedance thereof are adjustable
#414Data interface circuit for capturing received data bits including continuous calibration
#415Training of storage devices in computing systems and environments
#416Method and apparatus for determining status element total with sequentially coupled counting status circuits
#417Auto-calibration for high speed input/output
#418Method and apparatus for clock and data recovery
#419Output slew rate control
#420Buffer for managing data samples in a read channel
#421Low-pin-count non-volatile memory embedded in a integrated circuit without any additional pins for access
#422Drift tracking feedback for communication channels
#423Semiconductor memory, memory system, and operation method thereof
#424Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock drift
#425Semiconductor integrated circuit with switch to select single or multiple chips
#426Semiconductor device, adjustment method thereof and data processing system
#427Memory subsystem data bus stress testing
#428Semiconductor storage device and control method thereof
#429Three-dimensional flash memory system
#430SRAM with buffered-read bit cells and its testing
#431Apparatuses and methods for capturing data in a memory
#432Computer memory test structure
#433On-die termination of address and command signals
#434Semiconductor memory systems with on-die data buffering
#435Memory controller that enforces strobe-to-strobe timing offset
#436Method, system and apparatus for evaluation of input/output buffer circuitry
#437Probeless testing of pad buffers on wafer
#438Embedded multimedia card (eMMC), eMMC system, and methods of operation
#439Memory system having memory ranks and related tuning method
#440Chip capable of improving test coverage of pads and related method thereof
#441Output driver to drive semiconductor device and memory system
#442Technique for determining performance characteristics of electronic devices and systems
#443Data output circuit of semiconductor device
#444Semiconductor apparatus and test method thereof
#445Bit error testing and training in double data rate (DDR) memory system
#446Timing calibration for multimode I/O systems
#447Testing device
#448No-touch stress testing of memory I/O interfaces
#449Memory access alignment in a double data rate (‘DDR’) system
#450Methods and apparatus for testing inaccessible interface circuits in a semiconductor device
#451Simultaneous switching noise cancellation by adjusting reference voltage and sampling clock phase
#452Protocol for memory power-mode control
#453Data strobe control device
#454Method of sharing in use an impedance matching circuit of a memory circuit to perform an initial calibration and a full time refresh mode calibration, and memory circuit with an impedance matching circuit capable of being used in an initial calibration and a full time refresh mode calibration
#455Channel skewing
#456Method and apparatus for evaluating and optimizing a signaling system
#457Driver for DDR2/3 memory interfaces
#458Method of testing universal flash storage (UFS) interface and memory device implementing method of testing UFS interface
#459Semiconductor device including output circuit constituted of plural unit buffer circuits in which impedance thereof are adjustable
#460Semiconductor device having impedance calibration function to data output buffer and semiconductor module having the same
#461SEMICONDUCTOR SYSTEM
#462Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock drift
#463Measurement card
#464High speed multiple memory interface I/O cell
#465Adjustable data drivers and methods for driving data signals
#466Semiconductor memory device, semiconductor system including the semiconductor memory device, and method for operating the semiconductor memory device
#467Frequency-agile strobe window generation
#468I/O circuit with phase mixer for slew rate control
#469Measurement of latency in data paths
#470Apparatus and method for receiving a differential data strobe signal
#471Semiconductor device, adjustment method thereof and data processing system
#472Memory access alignment in a double data rate (‘DDR’) system
#473Pad switch cells selectively coupling test leads to test pads
#474Memory controller comprising adjustable transmitter impedance
#475Memory controller with selective data transmission delay
#476Method of detecting defects in a semiconductor device and semiconductor device using the same
#477Method of testing a semiconductor memory device
#478Output driver circuit, output driver system and semiconductor memory device
#479Semiconductor device having plural data buses and plural buffer circuits connected to data buses
#480High speed test circuit and method
#481Setting a reference voltage in a memory controller trained to a memory device
#482System and method for bonded configuration pad continuity check
#483Output circuit for semiconductor device, semiconductor device having output circuit, and method of adjusting characteristics of output circuit
#484Memory controller
#485Semiconductor device having plural penetration electrodes penetrating through semiconductor substrate and testing method thereof
#486Semiconductor device having calibration circuit for adjusting output impedance of output buffer circuit
#487Memory interface with selectable evaluation modes
#488Semiconductor memory device for transferring data at high speed
#489Control circuit and data hold device using the control circuit
#490Timing adjustment circuit for a memory interface and method of adjusting timing for memory interface
#491Method and apparatus for reducing oscillation in synchronous circuits
#492Output slew rate control
#493CIRCUIT AND METHOD FOR CORRECTING SKEW IN A PLURALITY OF COMMUNICATION CHANNELS FOR COMMUNICATING WITH A MEMORY DEVICE, MEMORY CONTROLLER, SYSTEM AND METHOD USING THE SAME, AND MEMORY TEST SYSTEM AND METHOD USING THE SAME
#494Memory diagnostics system and method with hardware-based read/write patterns
#495Method and apparatus for evaluating and optimizing a signaling system
#496High resolution output driver
#497Semiconductor device having level shift circuit
#498Reconfigurable connections for stacked semiconductor devices
#499Semiconductor device, adjustment method thereof and data processing system
#500Semiconductor device and information processing system including an input circuit with a delay
#501Scan path switch testing of output buffer with ESD
#502Method and Apparatus for Performing Memory Interface Calibration
#503Data strobe signal generation circuit
#504Apparatus for measuring data setup/hold time
#505Input/output circuit and method of semiconductor apparatus and system with the same
#506Data output buffer and memory device
#507VERIFYING A DATA PATH IN A SEMICONDUCTOR APPARATUS
#508Technique for determining performance characteristics of electronic devices and systems
#509Apparatus and method for data capture using a read preamble
#510TEST CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME
#511Latch based memory device
#512DRAM memory controller with built-in self test and methods for use therewith
#513Channel skewing
#514Memory systems and memory modules
#515Integrated semiconductor device
#516Adaptive flash interface
#517SRAM with buffered-read bit cells and its testing
#518Semiconductor device
#519Calibrating resistance for integrated circuit
#520Integrated circuit and method for controlling data output impedance
#521Input buffer circuit capable of adjusting variation in skew
#522Method and Circuit for Configuring Memory Core Integrated Circuit Dies with Memory Interface Integrated Circuit Dies
#523Setting a reference voltage in a memory controller trained to a memory device
#524Training a memory controller and a memory device using multiple read and write operations
#525Output apparatus and test apparatus
#526SEMICONDUCTOR APPARATUS
#527Methods for defect testing of externally accessible integrated circuit interconnects
#528Apparatus and method for testing shadow logic
#529Semiconductor memory device, semiconductor system including the semiconductor memory device, and method for operating the semiconductor memory device
#530Apparatus and methods for through substrate via test
#531Method and apparatus for reducing oscillation in synchronous circuits
#532Test circuit for input/output array and method and storage device thereof
#533Communication channel calibration with nonvolatile parameter store for recovery
#534System and method for controlling timing of output signals
#535Semiconductor memory device
#536Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock drift
#537SEMICONDUCTOR DEVICE AND CIRCUIT BOARD HAVING THE SEMICONDUCTOR DEVICE MOUNTED THEREON
#538Adjustment of write timing based on a training signal
#539Memory module including memory buffer and memory system having the same
#540Input buffer, test switches and switch control with serial I/O
#541Integrated solution for identifying malfunctioning components within memory devices
#542Skew detector and semiconductor memory device using the same
#543Data channel test apparatus and method thereof
#544Output slew rate control
#545Protocol sequence generator
#546Memory interface circuit
#547Method for adjusting memory signal phase
#548Impedance calibration circuit with uniform step heights
#549Semiconductor device, system with semiconductor device, and calibration method
#550Semiconductor device, adjustment method thereof and data processing system
#551High speed multiple memory interface I/O cell
#552Memory link initialization
#553Memory controller comprising adjustable transmitter impedance
#554System and method for controlling timing of output signals
#555Semiconductor device having a memory and calibration circuit that selectively adjusts an impedance of an output buffer dependent upon refresh commands
#556Memory controlling method
#557Memory chip and method for operating the same
#558Reconfigurable connections for stacked semiconductor devices
#559Testing device and method for SM memory connector
#560Computer memory test structure
#561Output circuit for semiconductor device, semiconductor device having output circuit, and method of adjusting characteristics of output circuit
#562Low-power source-synchronous signaling
#563I/O circuit with phase mixer for slew rate control
#564Semiconductor integrated circuit
#565Apparatus and method for compensating for process, voltage, and temperature variation of the time delay of a digital delay line
#566Double data rate memory physical interface high speed testing using self checking loopback
#567Method and apparatus for evaluating and optimizing a signaling system
#568Memory interface and operation method of it
#569Calibration of memory driver with offset in a memory controller and memory device interface in a communication bus
#570Setting controller VREF in a memory controller and memory device interface in a communication bus
#571Setting memory device termination in a memory device and memory controller interface in a communication bus
#572Semiconductor device
#573Operation guarantee system
#574Semiconductor device
#575Self-refresh based power saving circuit and method
#576Flash storage device and method and system for testing the same
#577Circuit and method for correcting skew in a plurality of communication channels for communicating with a memory device, memory controller, system and method using the same, and memory test system and method using the same
#578Method and apparatus for testing the connectivity of a flash memory chip
#579Method and apparatus for generating expect data from a captured bit pattern, and memory device using same
#580Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock drift
#581Interface for writing to memories having different write times
#582Drift tracking feedback for communication channels
#583Semiconductor memory device
#584Semiconductor memory apparatus
#585Automatic multicable electrical continuity tester
#586Memory test circuit which tests address access time of clock synchronized memory
#587On-die termination of address and command signals
#588Method and apparatus for reducing oscillation in synchronous circuits
#589Data readout circuit and semiconductor memory device
#590Apparatus and methods for through substrate via test
#591Systems and methods for defect testing of externally accessible integrated circuit interconnects
#592Read leveling of memory units designed to receive access requests in a sequential chained topology
#593Bit shadowing in a memory system
#594276-PIN BUFFERED MEMORY MODULE WITH ENHANCED MEMORY SYSTEM INTERCONNECT AND FEATURES
#595Apparatus for measuring data setup/hold time
#596System and method for an asynchronous data buffer having buffer write and read pointers
#597Memory chip and method for operating the same
#598Method and circuit for configuring memory core integrated circuit dies with memory interface integrated circuit dies
#599Calibration circuit
#600Method and apparatus for testing a random access memory device