ClassID:

199828

G11C29/824 - CPC Classification

Classification description:

Checking stores for correct operation ; Subsequent repair ; Testing stores during standby or offline operation; Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout for synchronous memories

Recent Application in this class:
#1
20240257863
2024-08-01

MEMORIES AND MEMORY COMPONENTS WITH INTERCONNECTED AND REDUNDANT DATA INTERFACES

#2
20220148643
2022-05-12

Memories and memory components with interconnected and redundant data interfaces

#3
20190378560
2019-12-12

Memories and memory components with interconnected and redundant data interfaces

#4
20190295645
2019-09-26

DRAM device with embedded flash memory for redundancy and fabrication method thereof

#5
20190221181
2019-07-18

Shift register unit and method for controlling the same, gate driving circuit, display device

#6
20190131308
2019-05-02

Peripheral logic circuits under DRAM memory arrays

#7
20190102313
2019-04-04

Techniques to store data for critical chunk operations

#8
20180286481
2018-10-04

DRAM device with embedded flash memory for redundancy and fabrication method thereof

#9
20180053544
2018-02-22

Memories and memory components with interconnected and redundant data interfaces

#10
20130080826
2013-03-28

SEMICONDUCTOR DEVICE VERIFYING SIGNAL SUPPLIED FROM OUTSIDE

#11
20120057414
2012-03-08

Data input circuit of nonvolatile memory device

#12
20110063933
2011-03-17

Semiconductor device, relief-address-information writing device, and relief-address-information writing method

#13
20110058445
2011-03-10

Latency counter, semiconductor memory device including the same, and data processing system

#14
20090161429
2009-06-25

Dynamic column redundancy replacement

#15
20090016092
2009-01-15

Semiconductor memory device and local input/output division method