199824 ⎘
Checking stores for correct operation ; Subsequent repair ; Testing stores during standby or offline operation; Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout
Sub-classes:Failover Methods and Systems in Three-Dimensional Memory Device
#2Failover methods and systems in three-dimensional memory device
#3Semiconductor memory devices and repair methods of the semiconductor memory devices
#4Apparatuses and methods for fuse latch redundancy
#5Redundancy array column decoder for memory
#6Peripheral logic circuits under DRAM memory arrays
#7On-the-fly bit failure detection and bit redundancy remapping techniques to correct for fixed bit defects
#8Forcing stuck bits, waterfall bits, shunt bits and low TMR bits to short during testing and using on-the-fly bit failure detection and bit redundancy remapping techniques to correct them
#9Apparatus and methods for through substrate via test
#10Semiconductor memory devices, methods of operating semiconductor memory devices and memory systems
#11Redundancy array column decoder for memory
#12Error correction code (ECC) decoders sharing logic operations, memory controllers including the error correction code decoders, and methods of decoding error correction codes
#13Redundancy array column decoder for memory
#14Semiconductor apparatus capable of improving efficiency for a circuit configuration and a signal line interconnection
#15Techniques to achieve area reduction through co-optimizing logic core blocks and memory redundancies
#16Apparatus and methods for through substrate via test
#17Fault-tolerance through silicon via interface and controlling method thereof
#18Three-port bit cell having increased width
#19Semiconductor memory device for controlling having different refresh operation periods for different sets of memory cells
#20Apparatus and methods for through substrate via test
#21DRAM repair architecture for wide I/O DRAM based 2.5D/3D system chips
#22Block mapping circuit and method for memory device
#23Semiconductor memory device
#24SEMICONDUCTOR MEMORY DEVICE
#25Apparatus and methods for through substrate via test
#26Semiconductor memory device having a redundancy memory cell array
#27Semiconductor memory device including repair redundancy memory cell arrays
#28Write-once nonvolatile memory with redundancy capability
#29Semiconductor memory device for compensating for operating voltage difference between near cell and far cell in consideration of cell position, and memory card and memory system including the same
#30TCAM BIST with redundancy
#31Apparatus and methods for through substrate via test
#32Methods and Apparatus for Translating a System Address
#33Method and apparatus for SRAM macro sparing in computer chips
#34Memory array peripheral structures and use
#35Redundant memory to mask DRAM failures
#36Electrical fuses with redundancy
#37Self-referencing redundancy scheme for a content addressable memory
#38Memory system with RAM array and redundant RAM memory cells having a different designed cell circuit topology than cells of non redundant RAM array
#39Fuse cell array with redundancy features
#40Dynamic random access memory (DRAM) for suppressing a short-circuit current
#41Integrated circuit device and electronic instrument
#42Thin film magnetic memory device having redundant configuration
#43Integrated circuit memory devices having multi-bit normal memory cells and single-bit redundant memory cells therein
#44Write-once nonvolatile memory with redundancy capability
#45Deterministic addressing of nanoscale devices assembled at sublithographic pitches
#46Semiconductor memory device with memory cells, each having bit registering layer in addition to a memory layer and method of driving the same
#47Ferroelectric random access memory
#48High granularity redundancy for ferroelectric memories
#49Thin film magnetic memory device having redundant configuration
#50Method and apparatus for programming a memory array
#51Device and method for configuring a cache tag in accordance with burst length
#52Method and apparatus for incorporating block redundancy in a memory array
#53TCAM BIST with redundancy
#54Electrical fuses with redundancy
#55Nonvolatile semiconductor memory device having improved redundancy relieving rate
#56Memory device having open bit line architecture for improving repairability and method of repairing the same
#57Semiconductor memory device and a method of redressing a memory cell
#58Semiconductor memory device
#59Isolation device over field in a memory device
#60Methods for repairing and for operating a memory component
#61Content addressable memory device
#62Enhanced functionality in a two-terminal memory array
#63Redundancy circuits and memory devices having a twist bitline scheme and methods of repairing defective cells in the same
#64Nonvolatile semiconductor memory device having improved redundancy relieving rate
#65Semiconductor storage device
#66Device and method for configuring a cache tag in accordance with burst length
#67Semiconductor integrated circuit device
#68Semiconductor memory device of bit line twist system
#69Random access memory with optional inaccessible memory cells
#70Thin film magnetic memory device having redundant configuration
#71Isolation device over field in a memory device
#72Byte aligned redundancy for memory array
#73Apparatuses and methods for fuse latch redundancy
#74Error handling for match action unit memory of a forwarding element
#75Error handling for match action unit memory of a forwarding element