207466 ⎘
Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof; Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof; Manufacture of specific parts of devices defined in group; Making of isolation regions between components; Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
#2SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
#3MIDDLE VOLTAGE TRANSISTOR WITH FIN STRUCTURE AND FABRICATING METHOD OF THE SAME
#4BACKSIDE TRENCH ISOLATION FOR HIGH VOLTAGE DEVICE INTEGRATION
#5SEMICONDUCTOR DEVICE WITH A FIRST ISOLATION TRENCH AND A SECOND ISOLATION TRENCH AND METHOD OF MANUFACTURING
#6SEMICONDUCTOR PROCESSING INTEGRATION FOR BIPOLAR JUNCTION TRANSISTOR (BJT)
#7FIELD EFFECT TRANSISTOR WITH DUAL LAYER ISOLATION STRUCTURE AND METHOD
#8METHODS FOR SEAM REPAIR AND SEMICONDUCTOR STRUCTURE MANUFACTURED THEREOF
#9SEMICONDUCTOR DEVICE
#10SEMICONDUCTOR STRUCTURE WITH JUNCTION LEAKAGE REDUCTION
#11TESTING STRUCTURE FOR AN INTEGRATED CHIP HAVING A HIGH-VOLTAGE DEVICE
#12DIELECTRIC FIN STRUCTURES WITH VARYING HEIGHT
#13Integrated Circuit with a Fin and Gate Structure and Method Making the Same
#14METHOD OF FORMING SEMICONDUCTOR DEVICE, ZERO-LAYER OVERLAY MARK AND METHOD OF FORMING THE SAME
#15SEMICONDUCTOR DEVICE HAVING A DUMMY SECTION AND METHOD FOR MANUFACTURING THE SAME
#16PLASMA PROCESSING DEVICE AND PLASMA PROCESSING METHOD USING SAME
#17SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
#18METHOD OF MANUFACTURING DEVICE ISOLATION LAYER AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE BY USING THE SAME
#19SEMICONDUCTOR DEVICE INCLUDING VIA STRUCTURE CONNECTED TO BACKSIDE POWER DELIVERY NETWORK
#20METHODS FOR IMPROVING DEPTH LOADING IN TRANSISTORS
#21SEMICONDUCTOR DEVICE AND METHOD OF FORMING THEREOF
#22SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
#23METHOD OF FORMING LINE PATTERN IN SEMICONDUCTOR DEVICE
#24ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME IN FIELD-EFFECT TRANSISTORS
#25Method for Thinning a Semiconductor Substrate
#26BACKSIDE FUSE CONNECTED TO BACKSIDE BACK END OF THE LINE NETWORK
#27DAM LAMINATE ISOLATION SUBSTRATE
#28METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
#29SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME
#30HIGH VOLTAGE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME
#31SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF AND MEMORY SYSTEM
#32ISOLATION STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
#33NANOSHEET HEIGHT CONTROL WITH DENSE OXIDE SHALLOW TRENCH ISOLATION
#34FIELD EFFECT TRANSISTOR WITH DUAL LAYER ISOLATION STRUCTURE AND METHOD
#35SEMICONDUCTOR DEVICE WITH DEEP TRENCH ISOLATION AND SHALLOW TRENCH ISOLATION AND FABRICATING METHOD OF THE SAME
#36Structure and Method for FinFET Device with Asymmetric Contact
#37Semiconductor Device and Method
#38Dummy Fin Structures and Methods of Forming Same
#39MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE
#40Semiconductor device and fabricating method of the same
#41SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
#42ARRAY BOUNDARY STRUCTURE TO REDUCE DISHING
#43SEMICONDUCTOR TRENCH CAPACITOR STRUCTURE AND MANUFACTURING METHOD THEREOF
#44Semiconductor Structure Cutting Process and Structures Formed Thereby
#45SEMICONDUCTOR FEATURE AND METHOD FOR MANUFACTURING THE SAME
#46DEEP TRENCH ISOLATIONS AND METHODS OF FORMING THE SAME
#47HYBRID ISOLATION REGIONS HAVING UPPER AND LOWER PORTIONS WITH SEAMS
#48SHALLOW TRENCH ISOLATION (STI) CONTACT STRUCTURES AND METHODS OF FORMING SAME
#49SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
#50METHOD OF FABRICATING A FINFET DEVICE
#51DEVICE OF DIELECTRIC LAYER
#52ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME
#53SEMICONDUCTOR DEVICE HAVING FINS AND METHOD OF FABRICATING THE SAME
#54SEMICONDUCTOR STRUCTURE WITH ISOLATION REGION INCLUDING COMBINATION OF DEEP AND SHALLOW TRENCH ISOLATION STRUCTURES AND METHOD
#55SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
#56METHODS FOR FORMING SEMICONDUCTOR STRUCTURE
#57Integrated circuit with a Fin and gate structure and method making the same
#58METHOD FOR PRODUCING A SEMICONDUCTIVE DEVICE COMPRISING A BACK GATE
#59HIGH VOLTAGE SEMICONDUCTOR DEVICE HAVING A DEEP TRENCH INSULATION AND MANUFACTURING PROCESS
#60DOPING FREE CONNECTION STRUCTURES AND METHODS
#61MERGED TRENCHES SURROUNDED BY WIDER TRENCH FOR ISOLATING SEMICONDUCTOR DEVICES
#62Shallow Trench Isolation Forming Method and Structures Resulting Therefrom
#63Method of fabricating semiconductor device
#64Semiconductor structure cutting process and structures formed thereby
#65FORMING METAL GATE CUTS USING MULTIPLE PASSES FOR DEPTH CONTROL
#66SELECTIVE ETCHES FOR REDUCING CONE FORMATION IN SHALLOW TRENCH ISOLATIONS
#67METHODS FOR SEAM REPAIR AND SEMICONDUCTOR STRUCTURE MANUFACTURED THEREOF
#68SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITHOUT FIN END GAP
#69SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR PREPARING THE SAME
#70METHOD FOR FORMING SEMICONDUCTOR STRUCTURE WITH HIGH ASPECT RATIO
#71MEMORY STRUCTURE, SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME
#72LOCOS OR SIBLK TO PROTECT DEEP TRENCH POLYSILICON IN DEEP TRENCH AFTER STI PROCESS
#73DIE SIZE REDUCTION AND DEEP TRENCH DENSITY INCREASE USING DEEP TRENCH ISOLATION AFTER SHALLOW TRENCH ISOLATION INTEGRATION
#74Hybrid isolation regions having upper and lower portions with seams
#75Microfluidic channels sealed with directionally-grown plugs
#76Method of manufacturing semiconductor device including isolation structure with nitridation layer
#77ELECTRONIC DEVICE MANUFACTURING METHOD
#78MULTIPLE CRITICAL DIMENSION POWER RAIL
#79SEMICONDUCTOR DEVICES
#80SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME
#81VERTICAL NON-VOLATILE MEMORY WITH LOW RESISTANCE SOURCE CONTACT
#82Isolation structures and methods of forming the same in field-effect transistors
#83Method for manufacturing a semiconductor device having a dummy section
#84Semiconductor device structure and method for preparing the same
#85SEMICONDUCTOR DEVICE
#86Semiconductor feature and method for manufacturing the same
#87Method of manufacturing multi-channel field effect transistors
#88Seal method to integrate non-volatile memory (NVM) into logic or bipolar CMOS DMOS (BCD) technology
#89Semiconductor trench capacitor structure and manufacturing method thereof
#90Semiconductor device and method of fabricating the same
#91THREE-DIMENSIONAL MEMORY DEVICES HAVING ISOLATION STRUCTURE FOR SOURCE SELECT GATE LINE AND METHODS FOR FORMING THE SAME
#92Array boundary structure to reduce dishing
#93SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
#94MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE INCLUDING FORMING A RECESS FILLING PATTERN
#95Dummy fin structures and methods of forming same
#96Blocking Structures on Isolation Structures
#97SEMICONDUCTOR STRUCTURE HAVING FINS
#98Backside power rails and power distribution network for density scaling
#99METHOD OF FABRICATING METAL MASK
#100METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING ENHANCED PATTERNING TECHNIQUES
#101Method of manufacturing semiconductor structure
#102TESTING STRUCTURE FOR AN INTEGRATED CHIP HAVING A HIGH-VOLTAGE DEVICE
#103Semiconductor device and method
#104Hybrid scheme for improved performance for P-type and N-type FinFETs
#105SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
#106Semiconductor device having fins and method of fabricating the same
#107SEMICONDUCTOR DEVICE
#108Semiconductor devices and methods for fabricating the same
#109Semiconductor trench capacitor structure and manufacturing method thereof
#110Metal mask having a plurality of strip-shaped structures
#111Dielectric fin structures with varying height
#112SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
#113Semiconductor structure cutting process and structures formed thereby
#114THROUGH TRENCH ISOLATION FOR DIE
#115Semiconductor device and method of fabricating the same having a second active region disposed at an outer side of a first active region
#116Dummy Fin Etch to Form Recesses in Substrate
#117Formation of hybrid isolation regions through recess and re-deposition
#118Method for forming semiconductor device having isolation structures with different thicknesses
#119Semiconductor feature and method for manufacturing the same
#120Gate electrodes with notches and methods for forming the same
#121Semiconductor devices
#122Multiple thickness semiconductor-on-insulator field effect transistors and methods of forming the same
#123Shallow trench isolation (STI) contact structures and methods of forming same
#124DEEP TRENCH PROTECTION
#125Semiconductor device and method for fabricating the same
#126Structure and method for FinFET device with asymmetric contact
#127Method for Manufacturing Shallow Trench Isolation
#128Semiconductor device
#129Isolation structures and methods of forming the same in field-effect transistors
#130Fin field effect transistor (FinFet) device structure and method for forming the same
#131Shallow trench isolation forming method and structures resulting therefrom
#132Semiconductor structure comprising regions having an isolation trench with a stepped bottom surface therebetween and method of forming the same
#133SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
#134Semiconductor device with multiple threshold voltages and method for fabricating the same
#135Semiconductor structure and manufacturing method thereof
#136SEMICONDUCTOR STRUCTURE WITH JUNCTION LEAKAGE REDUCTION
#137Semiconductor device with flowable layer
#138Semiconductor device and method of manufacturing the same
#139Co-integrated high voltage (HV) and medium voltage (MV) field effect transistors with defect prevention structures
#140Method of depositing silicon oxide films
#141Deep trench isolations and methods of forming the same
#142Deep trench isolation with segmented deep trench
#143Method of forming semiconductor memory device having saddle portion
#144Semiconductor device
#145Method of forming an array boundary structure to reduce dishing
#146SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
#147Semiconductor device including semiconductor liner and method for fabricating the same
#148Semiconductor device including trench isolation layer and method of forming the same
#149Three-dimensional memory devices having isolation structure for source select gate line and methods for forming the same
#150Method for forming a source/drain of a semiconductor device having an insulating stack in a recess structure
#151Method for preparing semiconductor memory device with air gaps between conductive features
#152Semiconductor structure having isolations between fins and comprising materials with different thermal expansion coefficients (CTE)
#153Gapfill of variable aspect ratio features with a composite PEALD and PECVD method
#154Semiconductor device and method for manufacturing the same
#155Method for preparing semiconductor device structure with fine patterns at different levels
#156Semiconductor device and method of fabricating the same
#157SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME
#158Semiconductor device with flowable layer and method for fabricating the same
#159Selective etches for reducing cone formation in shallow trench isolations
#160Shallow trench isolation forming method and structures resulting therefrom
#161Semiconductor manufacturing method
#162METHOD FOR PREPARING TRENCH ISOLATION STRUCTURE AND METHOD FOR PREPARING SEMICONDUCTOR DEVICE
#163Seal method to integrate non-volatile memory (NVM) into logic or bipolar CMOS DMOS (BCD) technology
#164Dummy fin structures and methods of forming same
#165Multiple thickness semiconductor-on-insulator field effect transistors and methods of forming the same
#166Shallow trench isolation (STI) contact structures and methods of forming same
#167Method for forming a semiconductor device having protrusion structures on a substrate and a planarized capping insulating layer on the protrusion structures
#168SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
#169Formation of hybrid isolation regions through recess and re-deposition
#170Field-effect transistor devices with sidewall implant under bottom dielectric isolation
#171Semiconductor device having isolation fins
#172Semiconductor memory device with air gaps between conductive features and method for preparing the same
#173Method of fabricating a FinFET device
#174Isolation structure having different distances to adjacent FinFET devices
#175Formation of contacts for semiconductor devices
#176Semiconductor device comprising a deep trench isolation structure and a trap rich isolation structure in a substrate and a method of making the same
#177Epitaxial growth constrained by a template
#178Integrated circuit with a fin and gate structure and method making the same
#179Device of dielectric layer
#180Semiconductor device structure with fine patterns at different levels and method for forming the same
#181Semiconductor device
#182Semiconductor device with dual isolation liner and method of forming the same
#183Dual trench isolation structures
#184Etch stop layer between substrate and isolation structure
#185Deep trench isolation and substrate connection on SOI
#186Semiconductor device and manufacturing method thereof
#187Semiconductor device and manufacturing method thereof
#188Method for forming semiconductor device having isolation structures with different thicknesses
#189FABRICATING METAL-OXIDE SEMICONDUCTOR DEVICE USING A POST-LINEAR-ANNEAL OPERATION
#190Dishing prevention dummy structures for semiconductor devices
#191Method of forming material film, integrated circuit device, and method of manufacturing the integrated circuit device
#192Process for integrated circuit fabrication using a buffer layer as a stop for chemical mechanical polishing of a coupled dielectric oxide layer
#193Blocking structures on isolation structures
#194POLISHING SLURRY COMPOSITION FOR STI PROCESS
#195Semiconductor devices and methods of fabricating the same
#196Semiconductor device and method of manufacturing the same
#197Method for forming recesses in a substrate by etching dummy fins
#198Process method for cutting polysilicon gate of FinFET transistor
#199Hybrid scheme for improved performance for P-type and N-type FinFETs
#200Method for manufacturing a semiconductor device having a dummy section
#201Self-aligned gate endcap (SAGE) architectures without fin end gap
#202APPARATUS WITH OVERLAPPING DEEP TRENCH AND SHALLOW TRENCH AND METHOD OF FABRICATING THE SAME WITH LOW DEFECT DENSITY
#203Method for forming isolation structure having improved gap-fill capability
#204Semiconductor device and method
#205Method of planarizing insulating layer for memory device
#206Method for manufacturing semiconductor device
#207Method for forming semiconductor structure with high aspect ratio
#208Deep trench protection
#209Method of forming a semiconductor device with a dual gate dielectric layer having middle portion thinner than the edge portions
#210Hybrid computing module
#211Method of depositing silicon oxide films
#212Source/drain features with an etch stop layer
#213Semiconductor device including trench isolation layer and method of forming the same
#214Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
#215Structure and method for FinFET device with asymmetric contact
#216Gap-fill method having improved gap-fill capability
#217Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
#218Heterojunction bipolar transistors having bases with different elevations
#219Semiconductor constructions comprising dielectric material, and methods of forming dielectric fill within openings extending into semiconductor constructions
#220Semiconductor devices and methods for fabricating the same
#221Semiconductor structures
#222SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
#223Semiconductor device
#224Hybrid scheme for improved performance for P-type and N-type FinFETs
#225Power metal-oxide-semiconductor field effect transistor
#226Semiconductor device having fins
#227Cyclic flowable deposition and high-density plasma treatment processes for high quality gap fill solutions
#228Semiconductor device
#229Method for fabricating semiconductor device
#230Semiconductor device and method for fabricating the same
#231Semiconductor structures
#232SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD FOR SAME
#233Semiconductor isolation structures comprising shallow trench and deep trench isolation
#234Semiconductor devices
#235Hybrid computing module
#236Semiconductor device
#237Non-volatile memory device and operation method thereof
#238Semiconductor device
#239Method for manufacturing semiconductor device including fin-structured transistor
#240Hybrid scheme for improved performance for P-type and N-type FinFETs
#241Semiconductor device and fabrication method thereof
#242FinFET device
#243Semiconductor structures and fabrication method thereof
#244Integrated circuit with a fin and gate structure and method making the same
#245Source/drain features with an etch stop layer
#246Device of dielectric layer
#247Isolation structure having different distances to adjacent FinFET devices
#248Semiconductor device and manufacturing method thereof
#249Self-aligned top spacers for vertical FETs with in situ solid state doping
#250FinFET devices and methods of forming the same
#251Dummy fin structures and methods of forming same
#252Semiconductor device and method
#253Etch stop layer between substrate and isolation structure
#254Semiconductor device with a stacked structure and a capping insulation layer
#255Dishing prevention dummy structures for semiconductor devices
#256Gate electrodes with notches and methods for forming the same
#257Semiconductor device and method for fabricating the same
#258Semiconductor structure
#259Seal method to integrate non-volatile memory (NVM) into logic or bipolar CMOS DMOS (BCD) technology
#260Forming conductive plugs for memory device
#261Integrated single diffusion break
#262Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
#263Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
#264Structure and method for FinFET device with asymmetric contact
#265Seal method to integrate non-volatile memory (NVM) into logic or bipolar CMOS DMOS (BCD) technology
#266Selective etches for reducing cone formation in shallow trench isolations
#267Method for fabricating semiconductor device comprising a deep trench isolation structure and a trap rich isolation structure in a substrate
#268Method of forming semiconductor material in trenches having different widths, and related structures
#269Integrated computing structures formed on silicon
#270DAM LAMINATE ISOLATION SUBSTRATE
#271Semiconductor device and method for fabricating the same
#272FinFET with curved STI
#273Structure and method for FinFET device with contact over dielectric gate
#274Sealed cavity structures with a planar surface
#275Floating gate fabrication method
#276Self-heating test structure
#277Semiconductor device having fins
#278Self-limiting fin spike removal
#279Self-limiting fin spike removal
#280Method of fabricating an integrated circuit with non-printable dummy features
#281Method for manufacturing a semiconductor device having a dummy section
#282Source/drain features with an etch stop layer
#283Gapfill of variable aspect ratio features with a composite PEALD and PECVD method
#284Silicon-on-insulator structure having bipolar stress, and manufacturing method therefor
#285Method of patterning target layer
#286Dishing prevention dummy structures for semiconductor devices
#287Integrated circuit structure having a crown-shaped semiconductor strip and an isolation region recessed in the substrate
#288Semiconductor device and method for manufacturing same
#289Power trench capacitor compatible with deep trench isolation process
#290Mitigation for FinFET technology using deep isolation
#291Oxidative volumetric expansion of metals and metal containing compounds
#292Apparatus with overlapping deep trench and shallow trench and method of fabricating the same with low defect density
#293Fin field effect transistor (finFET) device structure and method for forming the same
#294Three-dimensional memory device containing through-memory-level contact via structures and method of making the same
#295Self-limiting fin spike removal
#296Blocking structures on isolation structures
#297Isolation pillar first gate structures and methods of forming same
#298Semiconductor devices and methods for fabricating the same
#299Fin reveal forming STI regions having convex shape between fins
#300SEMICONDUCTOR DEVICE INCLUDING INSULATING LAYERS AND METHOD OF MANUFACTURING THE SAME