207468 ⎘
Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof; Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof; Manufacture of specific parts of devices defined in group; Making of isolation regions between components; Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
Method for Preparing a Gate Oxide Layer
#302Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures
#303METHOD FOR ADDING AN IMPLANT AT THE SHALLOW TRENCH ISOLATION CORNER IN A SEMICONDUCTOR SUBSTRATE
#304Method of forming isolation structure in semiconductor substrate
#305Isolation structures for integrated circuits and modular methods of forming the same
#306SEMICONDUCTOR DEVICE HAVING IMPRIVED ELECTRICAL CHARACTERISTICS AND METHOD OF MANUFACTURING THE SAME
#307Modular methods of forming isolation structures for integrated circuits
#308Trench isolation methods of semiconductor device
#309METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
#310Application of different isolation schemes for logic and embedded memory
#311Isolation structures for integrated circuits and modular methods of forming the same
#312SEMICONDUCTOR DEVICE HAVING ISOLATION REGION AND METHOD OF MANUFACTURING THE SAME
#313Method for manufacturing a semiconductor device including a shallow trench isolation structure
#314Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures
#315Trench isolation implantation
#316Semiconductor device and fabrication method thereof
#317Method of preparing a semiconductor substrate utilizing plural implants under an isolation region to isolate adjacent wells
#318Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures
#319CMOS devices adapted to reduce latchup and methods of manufacturing the same
#320Trench isolation structure having different stress
#321Trench isolation structure for a semiconductor device with reduced sidewall stress and a method of manufacturing the same
#322Latch-up prevention in semiconductor circuits
#323Latch-up prevention in semiconductor circuits
#324Prevention of latch-up among p-type semiconductor devices
#325Integrated circuit devices having active regions with expanded effective widths
#326Semiconductor device with stress reducing trench fill containing semiconductor microparticles in shallow trench isolation
#327Trench isolation structure having an implanted buffer layer
#328Bottle-shaped trench and method of fabricating the same
#329Low-leakage transistor and manufacturing method thereof
#330Method of fabricating a semiconductor device
#331AN ISOLATION REGION FOR USE IN A SEMICONDUCTOR DEVICE
#332Trench isolation for semiconductor devices
#333Trench isolation methods of semiconductor device
#334Method of forming trench isolation in a semiconductor device
#335Method for manufacturing semiconductor device and semiconductor device
#336Methods for forming channel stop for deep trench isolation prior to deep trench etch
#337Method to improve device isolation via fabrication of deeper shallow trench isolation regions
#338Application of different isolation schemes for logic and embedded memory
#339Narrow width effect improvement with photoresist plug process and STI corner ion implantation
#340Method for manufacturing a semiconductor device including a shallow trench isolation structure
#341Solid-state imaging device, method for manufacturing the same and interline transfer CCD image sensor
#342Semiconductor device channel termination
#343Isolation trench perimeter implant for threshold voltage control
#344Shallow trench isolation depth extension using oxygen implantation
#345Method of manufacturing a semiconductor device
#346Semiconductor device and method for fabricating the same
#347Methods for elimination of arsenic based defects in semiconductor devices with isolation regions
#348Method to design for or modulate the CMOS transistor threshold voltage using shallow trench isolation (STI)
#349Method to engineer the inverse narrow width effect (INWE) in CMOS technology using shallow trench isolation (STI)
#350Shallow trench isolation method
#351Random access memory (RAM) capacitor in shallow trench isolation with improved electrical isolation to overlying gate electrodes
#352Method of fabricating shallow trench isolation by ultra-thin simox processing
#353Method of manufacture for a trench isolation structure having an implanted buffer layer
#354Semiconductor integrated circuit device having improved punch-through resistance and production method thereof, semiconductor integrated circuit device including a low-voltage transistor and a high-voltage transistor
#355Radiation-tolerant integrated circuit device and method for fabricating
#356Substrate isolation in integrated circuits
#357Semiconductor device having dual isolation structure and method of fabricating the same
#358Strained channel transistor and methods of manufacture
#359Random access memory (RAM) capacitor in shallow trench isolation with improved electrical isolation to overlying gate electrodes
#360Method of dry etching semiconductor substrate to reduce crystal defects in a trench
#361Application of different isolation schemes for logic and embedded memory
#362Method for forming trench isolation in semiconductor device
#363Semiconductor devices and manufacturing methods thereof
#364Method for isolating semiconductor devices
#365Methods of forming wells in semiconductor devices
#366Substrate isolation in integrated circuits
#367Semiconductor device
#368Non-volatile memory manufacturing method using STI trench implantation
#369Method of fabricating semiconductor components through implantation and diffusion in a semiconductor substrate
#370MOS transistor having improved total radiation-induced leakage current
#371Method of making a MOS transistor having improved total radiation-induced leakage current
#372Application of different isolation schemes for logic and embedded memory
#373Method of doping sidewall of isolation trench
#374Methods for forming shallow trench isolation
#375Dual depth trench isolation
#376Method of forming well in semiconductor device
#377Narrow width effect improvement with photoresist plug process and STI corner ion implantation
#378Method of forming trench in semiconductor device
#379Semiconductor device with increased isolation breakdown voltage
#380Sinker to buried layer connection region for narrow deep trenches
#381Semiconductor device and fabrication method thereof
#382Anneal after trench sidewall implant to reduce defects
#383Forming doped regions in semiconductor strips
#384Method of manufacturing a reverse-blocking IGBT
#385Method for fabricating semiconductor device
#386Self-aligned trench isolation in integrated circuits
#387Image sensor with semiconductor trench isolation
#388Y-FET with self-aligned punch-through-stop (PTS) doping
#389Punch through stopper for semiconductor device
#390Stress memorization technique for strain coupling enhancement in bulk finFET device
#391finFETs containing improved strain benefit and self aligned trench isolation structures
#392Trench power MOSFET structure and fabrication method thereof