207492 ⎘
Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof; Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof; Manufacture of specific parts of devices defined in group; Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
Sub-classes:Integrated Circuit Package and Method
#2CONTACT PLUGS FOR SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME
#3METHOD FOR FORMING DIELECTRIC LINERS ON THROUGH GLASS VIAS
#4INTERCONNECT STRUCTURE, METHOD OF MANUFACTURING SAME, AND ELECTRONIC DEVICE INCLUDING SAME
#5MULTI-WAFER CAPPING LAYER FOR METAL ARCING PROTECTION
#6SEMICONDUCTOR DEVICE WITH CONNECTING STRUCTURE HAVING A DOPED LAYER AND METHOD FOR FORMING THE SAME
#7SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME
#8CARRIER STRUCTURE AND METHODS OF FORMING THE SAME
#9Multi-wafer capping layer for metal arcing protection
#10METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS
#11CONTACT PLUGS FOR SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME
#12SELECTIVE BOTTOMLESS GRAPHENE LINED INTERCONNECTS
#13Integrated Circuit Package and Method
#14Semiconductor device structure and methods of forming the same
#15SEMICONDUCTOR DEVICE WITH CONNECTING STRUCTURE HAVING A DOPED LAYER AND METHOD FOR FORMING THE SAME
#16PREVENTING ELECTRODE DISCONTINUATION ON MICRODEVICE SIDEWALL
#17DIELECTRIC LAYER SEPARATING A METAL PAD OF A THROUGH GLASS VIA FROM A SURFACE OF THE GLASS
#18Multi-wafer capping layer for metal arcing protection
#19Interconnect structures and methods of fabrication
#20PLANAR SLAB VIAS FOR INTEGRATED CIRCUIT INTERCONNECTS
#21Microelectronic devices and related methods of forming microelectronic devices
#22Integrated circuit package and method
#23Semiconductor device with connecting structure having a doped layer and method for forming the same
#24Planar slab vias for integrated circuit interconnects
#25Methods of forming microelectronic devices, and related microelectronic devices, and electronic systems
#26Integrated circuit package and method
#27Integrated capacitor with sidewall having reduced roughness
#28Multi-wafer capping layer for metal arcing protection
#29Contact plugs for semiconductor device
#30Interconnect structures and methods of fabrication
#31Multifunctional molecules for selective polymer formation on conductive surfaces and structures resulting therefrom
#32Devices including stair step structures, and related apparatuses and memory devices
#33Contact interlayer dielectric replacement with improved SAC cap retention
#34Apparatus with multidielectric spacers on conductive regions of stack structures, and related methods
#35Forming high carbon content flowable dielectric film with low processing damage
#36Methods of fabricating semiconductor devices
#37Top via back end of the line interconnect integration
#38Semiconductor device and method of forming the same
#39Semiconductor devices and methods of manufacturing the same
#40Vertically stacked CMOS with upfront M0 interconnect
#41Microelectronic assemblies having magnetic core inductors
#42Semiconductor device and method of manufacturing the same
#43Structure and method for interconnection
#44DEFECT FREE SILICON GERMANIUM (SiGe) EPITAXY GROWTH IN A LOW-K SPACER CAVITY AND METHOD FOR PRODUCING THE SAME
#45High-density metal-insulator-metal (MiM) capacitors
#46Electronic devices with components formed by late binding using self-assembled monolayers
#47Method of forming electrical contacts in layered structures
#48SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
#49Memory devices and related methods
#50Method of forming a device having a doping layer and device formed
#51Method of forming contact plugs for semiconductor device
#52ETCHING METHOD AND ETCHING APPARATUS
#53Semiconductor device including a leveling dielectric fill material
#54COMPOUND SEMICONDUCTOR FIELD EFFECT TRANSISTOR WITH SELF-ALIGNED GATE
#55GATE CUT METHOD FOR REPLACEMENT METAL GATE
#56Semiconductor device and manufacturing method thereof
#57Integrated circuit and manufacturing method thereof
#58Graphene as interlayer dielectric
#59Electronic devices with components formed by late binding using self-assembled monolayers
#60Compound semiconductor field effect transistor with self-aligned gate
#61Method of forming a device having a doping layer and device formed
#62Through via structure and manufacturing method thereof
#63Airgap formation with damage-free copper
#64Stair step formation using at least two masks
#65Self-formed liner for interconnect structures
#66Semiconductor devices having interconnection structure
#67Interconnect arrangement with stress-reducing structure and method of fabricating the same
#68Semiconductor device and manufacturing method thereof
#69Simultaneous formation of liner and metal conductor
#70Calibration kits for RF passive devices
#71Structure and method for interconnection
#72Interconnect structure for semiconductor devices
#73Method of forming semiconductor device having dielectric layer and related system
#74Stair step formation using at least two masks
#75Chemoepitaxy-based directed self assembly process with tone inversion for unidirectional wiring
#76Interconnect arrangement with stress-reducing structure and method of fabricating the same
#77Method of forming metal nanostructure-based structure
#78Interconnect structure for semiconductor devices
#79UNIQUE BI-LAYER ETCH STOP TO PROTECT CONDUCTIVE STRUCTURES DURING A METAL HARD MASK REMOVAL PROCESS AND METHODS OF USING SAME
#80Method for forming interconnects
#81Calibration kits for RF passive devices
#82Non-lithographically patterned directed self assembly alignment promotion layers
#83Techniques for forming interconnects in porous dielectric materials
#84Air-gap scheme for BEOL process
#85Non-lithographically patterned directed self assembly alignment promotion layers
#86METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
#87Low-k dielectric pore sealant and metal-diffusion barrier formed by doping and method for forming the same
#88Interlayer dielectric layer with two tensile dielectric layers
#89Interconnect arrangement with stress-reducing structure and method of fabricating the same
#90Method for fabricating interlayer dielectric layer
#91Method for providing a self-aligned pad protection in a semiconductor device
#92Stair step formation using at least two masks
#93Method for forming interconnects
#94Air gap forming techniques based on anodic alumina for interconnect structures
#95Air-gap scheme for BEOL process
#96Nano deposition and ablation for the repair and fabrication of integrated circuits
#97Interconnect arrangement with stress-reducing structure and method of fabricating the same
#98Air gap forming techniques based on anodic alumina for interconnect structures
#99METHOD FOR FORMING THROUGH WAFER VIAS IN SEMICONDUCTOR DEVICES
#100Semiconductor devices and methods of fabricating the same
#101Method and apparatus for stacked semiconductor chips
#102Electrostatic discharge protection structure and method for forming the same
#103Semiconductor device and manufacturing method thereof
#104VBD AND TDDB IMPROVEMENT THRU INTERFACE ENGINEERING
#105Plasma etching method
#106Method of fabricating semiconductor device
#107Reliable interconnect for semiconductor device
#108Production of adhesion structures in dielectric layers using photoprocess technology and devices incorporating adhesion structures
#109Stair step formation using at least two masks
#110Calibration kits for RF passive devices
#111Semiconductor structure having etch stop layer
#112Corrugated interfaces for multilayered interconnects
#113Methods of forming wirings in electronic devices
#114Reduction of pore fill material dewetting
#115Semiconductor structure and method of manufacturing
#116Reduction of pore fill material dewetting
#117Overburden removal for pore fill integration approach
#118SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
#119Method for manufacturing a semiconductor device having an interconnect structure and a reinforcing insulating film
#120Semiconductor device and manufacturing method thereof
#121Method of manufacturing semiconductor devices
#122Semiconductor device and method of manufacturing the same
#123Reliable interconnect for semiconductor device
#124METHOD FOR MAKING INTEGRATED CIRCUIT DEVICE
#125METHOD OF PRODUCING SEMICONDUCTOR DEVICE
#126Etching method, semiconductor and fabricating method for the same
#127Method for manufacturing semiconductor device, semiconductor device, semiconductor manufacturing apparatus and storage medium
#128Semiconductor device and method of manufacturing the same
#129Film forming method for a semiconductor
#130Photosensitive resin composition, insulating film, protective film, and electronic equipment
#131Doped Layers for Reducing Electromigration
#132Fabrication of a diffusion barrier cap on copper containing conductive elements
#133Semiconductor device having an interconnect structure and a reinforcing insulating film
#134Ferroelectric capacitor with underlying conductive film
#135Semiconductor device and manufacturing method thereof
#136SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
#137Method for fabricating a semiconductor device
#138Method of forming capping structures on one or more material layer surfaces
#139Semiconductor device and method of manufacturing the same
#140Process integration scheme to lower overall dielectric constant in BEoL interconnect structures
#141Method for fabricating a semiconductor device that includes processing an insulating film to have an upper portion with a different composition than an other portion
#142Semiconductor device and method of fabricating same
#143Corrugated interfaces for multilayered interconnects
#144Film forming method for a semiconductor
#145Method of fabricating gate structure
#146Self-aligned dielectric cap
#147BEOL interconnect structures with improved resistance to stress
#148GATE STRUCTURE
#149Process integration scheme to lower overall dielectric constant in BEoL interconnect structures
#150Semiconductor device and method of producing the same
#151GCIB Cluster Tool Apparatus and Method of Operation
#152Copper interconnect wiring and method and apparatus for forming thereof
#153Semiconductor structure
#154Bi-layer etch stop process for defect reduction and via stress migration improvement
#155Method of fabricating gate structure
#156Semiconductor device and method of fabricating the same
#157Nitrous oxide anneal of TEOS/ozone CVD for improved gapfill
#158Semiconductor device having an interconnect structure and a reinforcing insulating film
#159Method for damascene process
#160Cap layer on doped dielectric
#161Semiconductor device and method of fabricating the same
#162Semiconductor device and manufacturing method thereof
#163Method of forming a semiconductor device having a diffusion barrier stack and structure thereof
#164Layered films formed by controlled phase segregation
#165Methods for making dual-damascene dielectric structures
#166Copper interconnect wiring and method of forming thereof
#167Semiconductor device and method of fabricating the same
#168Method for forming a multi-layer low-K dual damascene
#169Polyorganosiloxane dielectric materials
#170Nitrogen-free ARC/capping layer and method of manufacturing the same
#171Method of relieving wafer stress
#172Gradient low k material
#173Method for fabricating semiconductor device
#174Methods for manufacturing a soft error and defect resistant pre-metal dielectric layer
#175Bi-layer etch stop process for defect reduction and via stress migration improvement
#176Method for fabricating a dual damascene contact in an insulating film having density gradually varying in the thickness direction
#177Etching method, semiconductor and fabricating method for the same
#178Concentration graded carbon doped oxide
#179Method for forming flowable dielectric layer in semiconductor device
#180Method for forming flowable dielectric layer in semiconductor device
#181Dielectric liners on through glass vias
#182Multi-buried ULK field in BEOL structure
#183Self-formed liner for interconnect structures
#184Formation of liner and metal conductor
#185Simultaneous formation of liner and metal conductor