207503 ⎘
Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof; Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof; Manufacture of specific parts of devices defined in group; Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
Sub-classes:METHOD OF FORMING A PATTERNED LAYER OF MATERIAL, APPARATUS FOR FORMING A PATTERNED LAYER OF MATERIAL
#2Integrated Circuit Package and Method
#3SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
#4MICROELECTRONIC DEVICES INCLUDING SUPPORT PILLARS, AND RELATED MEMORY DEVICES
#5SEMICONDUCTOR DEVICE WITH INDUCTIVE COMPONENT AND METHOD OF FORMING
#6SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
#7SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
#8BACKSIDE SIGNAL INTERCONNECTION
#9INTEGRATED CIRCUIT PROVIDING POWER GATING AND METHOD OF DESIGNING THE SAME
#10SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
#11THREE DIMENSIONAL MEMORY AND METHODS OF FORMING THE SAME
#12SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
#13MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE
#14INTERCONNECT WIRES INCLUDING RELATIVELY LOW RESISTIVITY CORES
#15PHOTORESIST COMPOSITION AND METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE USING THE SAME
#16SRAM CELL WORD LINE STRUCTURE WITH REDUCED RC EFFECTS
#17SEMICONDUCTOR DIE AND METHOD FOR FORMING THE SAME
#18GATE-TIE-DOWN IN BACKSIDE POWER ARCHITECTURE USING TRENCH-TIE-DOWN SCHEME
#19METAL TIP-TO-TIP SCALING
#20Semiconductor device with uneven electrode surface and method for fabricating the same
#21METHODS FOR IMPROVING PASSIVATION LAYER DURABILITY
#22VERTICAL METAL SPLITTING USING HELMETS AND WRAP-AROUND DIELECTRIC SPACERS
#23METHOD OF FORMING MARK ON SEMICONDUCTOR DEVICE
#24METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
#25SEMICONDUCTOR DEVICE PACKAGES, PACKAGING METHODS, AND PACKAGED SEMICONDUCTOR DEVICES
#26METAL-INSULATOR-METAL CAPACITORS WITH THICK INTERMEDIATE ELECTRODE LAYERS AND METHODS OF FORMING THE SAME
#27METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE SAME
#28CAPACITOR EMBEDDING FOR FLIP CHIP PACKAGES
#29CHIP-SCALE PACKAGE ARCHITECTURES CONTAINING A DIE BACK SIDE METAL AND A SOLDER THERMAL INTERFACE MATERIAL
#30PLATING METHOD AND PLATING APPARATUS
#31SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
#32MITIGATING PATTERN COLLAPSE
#33SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
#34MICROELECTRONIC DEVICES AND MEMORY DEVICES INCLUDING SUPPORT PILLARS
#35Interconnect wires including relatively low resistivity cores
#36Semiconductor device and method for fabricating the same
#37Semiconductor device and method for fabricating the same
#38Display substrate, display panel and manufacturing method of display substrate
#39Metal-insulator-metal capacitors with thick intermediate electrode layers and methods of forming the same
#40Semiconductor device and method for manufacturing the same
#41SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
#42Three dimensional memory and methods of forming the same
#43MULTIPLE CRITICAL DIMENSION POWER RAIL
#44Semiconductor Device and Method of Providing High Density Component Spacing
#45INTERCONNECT STRUCTURE HAVING DIFFERENT DIMENSIONS FOR CONNECTED CIRCUIT BLOCKS IN INTEGRATED CIRCUIT
#46Semiconductor device packages, packaging methods, and packaged semiconductor devices
#47Method of manufacturing semiconductor device
#48INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD OF THE SAME
#49Integrated Circuit Package and Method
#50Semiconductor device and method for fabricating the same
#51SRAM cell word line structure with reduced RC effects
#52SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
#53METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
#54Backside signal interconnection
#55SEMICONDUCTOR DEVICE WITH INDUCTIVE COMPONENT AND METHOD OF FORMING
#56SECONDARY ELECTRON GENERATING COMPOSITION
#57Semiconductor device with uneven electrode surface and method for fabricating the same
#58Semiconductor devices and methods of forming semiconductor devices
#59Metal-insulator-metal (MIM) capacitor module including a cup-shaped structure with a rounded corner region
#60Interconnect structure for logic circuit
#61Semiconductor chip with fuse structure in scribe lane and method of fabricating the same
#62LEADED SEMICONDUCTOR PACKAGE FORMATION USING LEAD FRAME WITH STRUCTURED CENTRAL PAD
#63THREE DIMENSIONAL (3D) MEMORY DEVICE AND FABRICATION METHOD USING SELF-ALIGNED MULTIPLE PATTERNING AND AIRGAPS
#64Interconnect wires including relatively low resistivity cores
#65Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
#66METHODS FOR PRE-DEPOSITION TREATMENT OF A WORK-FUNCTION METAL LAYER
#67Semiconductor device with uneven electrode surface and method for fabricating the same
#68Standard cell design architecture for reduced voltage droop utilizing reduced contacted gate poly pitch and dual height cells
#69CONDUCTIVE AND FLEXIBLE SANDWICH-STRUCTURED COMPOSITES
#70Metal-insulator-metal capacitor with top contact
#71SEMICONDUCTOR DEVICE WITH DIGITAL ISOLATOR CAPACITOR AND MANUFACTURING METHOD THEREOF
#72Semiconductor device and manufacturing method thereof
#73HIGH-SPEED 3D METAL PRINTING OF SEMICONDUCTOR METAL INTERCONNECTS
#74Semiconductor device and method for fabricating the same
#75Semiconductor device and method for fabricating the same
#76Semiconductor device with interconnect part and method for preparing the same
#77Microelectronic devices including support pillar structures, and related memory devices
#78Dummy structure of stacked and bonded semiconductor device
#79Manufacturing method of semiconductor device
#80Semiconductor device and method for manufacturing the same
#81Metal-insulator-metal capacitors and methods of forming the same
#82Forming self-aligned multi-metal interconnects
#83HIGH VOLTAGE TRANSISTOR WITH A FIELD PLATE
#84Semiconductor device protection using an anti-reflective layer
#85Semiconductor device packages, packaging methods, and packaged semiconductor devices
#86SEMICONDUCTOR DEVICE AND METHOD OF FORMING PATTERNS FOR A SEMICONDUCTOR DEVICE
#87Method of manufacturing semiconductor device
#88Vertical metal splitting using helmets and wrap-around dielectric spacers
#89Semiconductor devices and preparation methods thereof
#90Integrated circuit package and method
#91Fabrication and use of through silicon vias on double sided interconnect device
#92Backside signal interconnection
#93Chip-scale package architectures containing a die back side metal and a solder thermal interface material
#94Conductive route patterning for electronic substrates
#95Metal oxide nanoparticles as fillable hardmask materials
#96Contact structures having conductive portions in substrate in three-dimensional memory devices and methods for forming the same
#97Interconnection for memory electrodes
#98Metal gate structure and method of fabricating the same
#99Metal gate structure and method of fabricating the same
#100Manufacturing method for graphene film, porous silica powder and transparent conductive layer
#101Semiconductor device with connecting structure and method for fabricating the same
#102Semiconductor device package and method of manufacturing the same
#103Semiconductor structure and manufacturing method thereof
#104Microelectronic devices including stair step structures, and related memory devices, electronic systems, and methods
#105SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
#106Substrate comprising a high-density interconnect portion embedded in a core layer
#107Method of manufacturing conductive lines in a circuit
#108Method for manufacturing semiconductor structure same
#109Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
#110Semiconductor device and manufacturing method thereof
#1113D IC method and device
#112Semiconductor device and method of providing high density component spacing
#113Semiconductor storage device including a memory cell array and manufacturing method of the same
#114Inorganic dies with organic interconnect layers and related structures
#115Stress analysis method and semiconductor device manufacturing method
#116INTEGRATED CIRCUIT COMPRISING AN INTERCONNECTION PART INCLUDING A PROTRUDING SOLDER ELEMENT AND CORRESPONDING PRODUCTION METHOD
#117Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
#118Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
#119Interconnection structure having reduced capacitance
#1203D IC method and device
#121SRAM cell word line structure with reduced RC effects
#122Back-end-of-line interconnect structures with varying aspect ratios
#123SEMICONDUCTOR DEVICE WITH CONNECTING STRUCTURE AND METHOD FOR FABRICATING THE SAME
#124Semiconductor devices and methods of forming semiconductor devices
#125Integrated circuit package and method
#126Fin field effect transistor (FinFET) device structure with isolation layer and method for forming the same
#127Mitigating pattern collapse
#128Semiconductor packages without debris
#129INORGANIC DIES WITH ORGANIC INTERCONNECT LAYERS AND RELATED STRUCTURES
#130Inorganic dies with organic interconnect layers and related structures
#131Three dimensional memory and methods of forming the same
#132Method of manufacturing a semiconductor package including correcting alignment error while forming redistribution wiring struture
#133Power Distribution
#134Contact structures having conductive portions in substrate in three-dimensional memory devices and methods for forming the same
#135Semiconductor devices having through electrodes and methods for fabricating the same
#136SYSTEM AND METHOD FOR INTERCONNECTION
#137Metal Wiring and Method of Manufacturing the Same, and Metal Wiring Substrate and Method of Manufacturing the Same
#138Interconnect structure and method
#139Frame-array interconnects for integrated-circuit packages
#140Interconnect wires including relatively low resistivity cores
#141Method for testing a high voltage transistor with a field plate
#142Semiconductor device and method for manufacturing the same
#143Semiconductor structure and method for manufacturing the same
#144Methods used in the fabrication of integrated circuitry
#145Forming self-aligned multi-metal interconnects
#146Adjusting reactive components
#147Method of forming and packaging semiconductor die
#148WIRING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
#149SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
#150Single process for liner and metal fill
#151Amorphous metal hot electron transistor
#152Interconnection for memory electrodes
#153Semiconductor device package and method of manufacturing the same
#154Method of filling grooves and holes in a substrate
#155Secondary electron generating composition
#156Semiconductor devices including support patterns
#157Copper passivation
#158Semiconductor device and method of forming patterns for a semiconductor device
#159Metal gate structure and method of fabricating the same
#160Dummy structure of stacked and bonded semiconductor device
#161Semiconductor device and method for fabricating the same
#162Atomic layer deposition and physical vapor deposition bilayer for additive patterning
#163Three-dimensional memory devices and fabricating methods thereof
#164Method of manufacturing semiconductor device
#165Nanowires with magnetic coatings and methods for making and using
#166Three dimensional memory and methods of forming the same
#167Semiconductor device and method for manufacturing the same
#168Interconnect structure for logic circuit
#169Electrochemical doping of thin metal layers employing underpotential deposition and thermal treatment
#170Antifuse array and method of forming antifuse using anodic oxidation
#171CIRCUIT DEVICE PROVIDED WITH CIRCUIT BOARD AND CIRCUIT COMPONENT, AND METHOD FOR MANUFACTURING SAID CIRCUIT DEVICE
#172Method of semiconductor integrated circuit fabrication
#173Single crystal silicon carbide substrate, method of manufacturing single crystal silicon carbide substrate, and semiconductor laser
#174Programming reactive components
#175Semiconductor power device and manufacturing method thereof
#176Connecting techniques for stacked substrates
#177Connection structure for stacked substrates
#178Semiconductor device packages, packaging methods, and packaged semiconductor devices
#179SRAM cell word line structure with reduced RC effects
#180Guard ring structure for an integrated circuit
#181Methods and systems for spin-coating multi-layer thin films having liquid conservation features
#182Semiconductor device having one or more titanium interlayers and method of making the same
#183Wiring structure and semiconductor device
#184Semiconductor device and manufacturing method thereof
#185Methods of forming integrated circuits having parallel conductors
#186Integrated circuits having parallel conductors
#187Method of manufacturing conductive lines in a circuit
#188Amorphous metal hot electron transistor
#189Spin-On Metallization
#190Interconnect structure for logic circuit
#191Metal interconnect fuse memory arrays
#192Semiconductor devices including support patterns
#193Semiconductor device and method for manufacturing same
#194Semiconductor devices having through electrodes and methods for fabricating the same
#195Stretchable film assembly with conductive traces
#196Vertical transistor static random access memory cell
#197Methods of forming semiconductor devices
#198Microelectronic devices including two contacts
#199Interconnect structure and method
#200Increased contact alignment tolerance for direct bonding
#201Hybrid copper structure for advance interconnect usage
#202SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
#203Package and method for integration of heterogeneous integrated circuits
#204Metal oxide nanoparticles as fillable hardmask materials
#205Dissimilar material interface having lattices
#206Lattice bump interconnect
#207Ultrasonic transducers in complementary metal oxide semiconductor (CMOS) wafers and related apparatus and methods
#208Three-dimensional memory devices and fabricating methods thereof
#209Single process for linear and metal fill
#210Fin field effect transistor (FinFET) device structure with isolation layer and method for forming the same
#2113D IC method and device
#212Semiconductor device having one or more titanium interlayers and method of making the same
#213Integration of single crystalline transistors in back end of line (BEOL)
#214Metal on both sides with clock gated-power and signal routing underneath
#215Methods of forming semiconductor devices
#216Seam healing of metal interconnects
#217METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
#218Chemoepitaxy etch trim using a self aligned hard mask for metal line to via
#219Composite member and method of manufacturing the same, and aliphatic polycarbonate-containing layer
#220Semiconductor device and manufacturing method thereof
#221Substrate conductor structure and method
#222Inkjet printing system and method for processing substrates
#223Methods and systems for spin-coating multi-layer thin films having liquid conservation features
#224Interconnection for memory electrodes
#225Three dimensional memory and methods of forming the same
#226Etching solution for copper and copper alloy surfaces
#227Magnetic trap for cylindrical diamagnetic materials
#228Directed self-assembly of block copolymers
#229Semiconductor device and method for manufacturing the same
#230Integrated vertical nanowire memory
#231Semiconductor package and semiconductor process
#232Mitigating pattern collapse
#233Method of making fully molded peripheral package on package device
#234Fabrication and use of through silicon vias on double sided interconnect device
#235Semiconductor device with multi-layer metallization
#236Methods of forming a semiconductor device comprising first and second nitride layers
#237Semiconductor device packages, packaging methods, and packaged semiconductor devices
#238Parallel plate waveguide for power semiconductor package
#239Power semiconductor package having a parallel plate waveguide
#240SYSTEM FOR PRE-DEPOSITION TREATMENT OF A WORK-FUNCTION METAL LAYER
#241Integrated circuits having parallel conductors and their formation
#242Methods of forming patterns using photomask including light-shielding portion having a recessed portion
#243Metal wiring and method of manufacturing the same, and metal wiring substrate and method of manufacturing the same
#244Method of semiconductor integrated circuit fabrication
#245Antifuse array and method of forming antifuse using anodic oxidation
#246Power distribution
#247Method of manufacturing semiconductor device
#248Increased contact alignment tolerance for direct bonding
#249Water assisted highly pure ruthenium thin film deposition
#250Structure and method to reduce copper loss during metal cap formation
#251Semiconductor device structures including stair step structures, and related semiconductor devices
#252Power semiconductor packages having a substrate with two or more metal layers and one or more polymer-based insulating layers for separating the metal layers
#253Semiconductor devices including support patterns
#254Semiconductor device, method of designing a layout of a semiconductor device, and method of manufacturing a semiconductor device
#255Field-effect transistors with a buried body contact
#256Fan-out semiconductor package
#257Package and method for integration of heterogeneous integrated circuits
#258Ultrasonic transducers in complementary metal oxide semiconductor (CMOS) wafers and related apparatus and methods
#259Semiconductor devices including stair-step structures
#260Package structure having under ball release layer and manufacturing method thereof
#261Semiconductor devices including conductive lines and methods of forming the semiconductor devices
#262Connecting techniques for stacked CMOS devices
#263SEMICONDUCTOR DEVICE AND A METHOD FOR FORMING A SEMICONDUCTOR DEVICE
#264Method, apparatus, and system for two-dimensional power rail to enable scaling of a standard cell
#265Hybrid copper structure for advance interconnect usage
#266Interconnect structure having subtractive etch feature and damascene feature
#267Methods for producing semiconductor devices
#268Semiconductor device and method of manufacturing a semiconductor device
#269Selective formation of metallic films on metallic surfaces
#270Three dimensional memory and methods of forming the same
#271Semiconductor device having a large area interconnect or pad
#272Semiconductor device and manufacturing method thereof
#273Top contact resistance measurement in vertical FETS
#274Activation method for silicon substrates comprising at least two aromatic acids
#275Semiconductor devices and methods of formation thereof
#276Method of forming conductive lines in circuits
#277Integrated circuit package stack
#278PHOTOMASK LAYOUTS AND METHODS OF FORMING PATTERNS USING THE SAME
#279FILM-EDGE TOP ELECTRODE
#280Interconnect wires including relatively low resistivity cores
#281Interconnect structure and method
#282Interconnection for memory electrodes
#283Biosensor for electrical detection of a nucleotide sequence
#284Methods for hybrid wafer bonding integrated with CMOS processing
#285Manganese barrier and adhesion layers for cobalt
#2863D IC method and device
#287Chip scale light emitting device package with dome
#288Semiconductor structure having etching stop layer and manufacturing method of the same
#289Single process for liner and metal fill
#290Semiconductor device including standard cell and electronic design automation method thereof
#291Interconnect structure and method
#292Semiconductor device and a method for forming a semiconductor device
#293Electronic device package and manufacturing method thereof
#294Method for a stacked and bonded semiconductor device
#295Columnar interconnects and method of making them
#296FULLY MOLDED PERIPHERAL PACKAGE ON PACKAGE DEVICE
#297Interconnect structure having substractive etch feature and damascene feature
#298Integrated vertical nanowire memory
#299Method of manufacturing semiconductor device
#300Method for fabricating a memory device having two contacts