Metal oxide semiconductor (MOS) transistor including a planarized material layer and method of fabricating the same

EEPROM device with substrate hot-electron injector for low-power programming

Semiconductor device

Body contact layout for semiconductor-on-insulator devices

Ultra-thin Si channel CMOS with improved series resistance

Method and circuit for multiplying signals with a transistor having more than one independent gate structure

Oxide/nitride stacked in FinFET spacer process

Selfaligned source/drain FinFET process flow

Semiconductor device having patterned SOI structure and method for fabricating the same

Semiconductor memory device for storing data as state of majority carriers accumulated in channel body and method of manufacturing the same

FinFET SRAM cell using low mobility plane for cell stability and method for forming

Methods of fabricating semiconductor-on-insulator (SOI) substrates and semiconductor devices using sacrificial layers and void spaces

Semiconductor memory device with plural source/drain regions

Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers

Semiconductor substrate and method for fabricating the same

Semiconductor device having SOI construction

Method of forming field effect transistor and structure formed thereby

Semiconductor device including transistors formed in semiconductor layer having single-crystal structure isolated from substrate

Method for manufacturing a semiconductor device

Semiconductor device and method of manufacturing the same

NROM flash memory devices on ultrathin silicon

Method and process to make multiple-threshold metal gates CMOS technology

Silicon device on Si:C-OI and SGOI and method of manufacture

High-density split-gate FinFET

Bipolar transistor, BiCMOS device, and method for fabricating thereof

High temperature memory device

High temperature imaging device

SOI chip with mesa isolation and recess resistant regions

Semiconductor device having a trench isolation and method of fabricating the same

Semiconductor memory device and its production process

Transistor structure with thick recessed source/drain structures and fabrication process of same

Semiconductor device having thin film transistor with position controlled channel formation region

Element fabrication substrate

Method of manufacturing semiconductor device

Systems and methods for integration of heterogeneous circuit devices

Semiconductor-on-insulator chip with<100>-oriented transistors

Oxidation method for altering a film structure and CMOS transistor structure formed therewith

Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors

Semiconductor device using partial SOI substrate and manufacturing method thereof

SOI component with increased dielectric strength and improved heat dissipation

Semiconductor device and manufacturing method of semiconductor device

Field effect transistor and manufacturing method thereof

Semiconductor device and method for fabricating the same

Single and double-gate pseudo-FET devices for semiconductor materials evaluation

Method and manufacture of thin silicon on insulator (SOI) with recessed channel

Strained Si/SiGe/SOI islands and processes of making same

Semiconductor device including a capacitance

Process integration of SOI FETs with active layer spacer

Method of manufacturing strained dislocation-free channels for CMOS

High performance strained CMOS devices

Semiconductor memory device having full depletive type logic transistors and partial depletion type memory transistors

Semiconductor integrated circuit device and semiconductor memory using the same

Double silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) structures

Vertically wired integrated circuit and method of fabrication

Semiconductor memory device and method of manufacturing the same

Fully depleted silicon-on-insulator CMOS logic

Static random access memories including a silicon-on-insulator substrate

Shallow trench isolation (STI) region with high-K liner and method of formation

High-density split-gate FinFET

TFT mask ROM and method for making same

Semiconductor layer formation

Method of manufacturing SOI template layer

Template layer formation

Hybrid integrated circuit device and method of manufacturing the same

Silicide proximity structures for CMOS device performance improvements

High performance voltage control diffusion resistor

Semiconductor device

Processes of forming stacked resistor constructions

Laser-irradiated thin films having variable thickness

Silicon on insulator device and layout method of the same

MOSFET performance improvement using deformation in SOI structure

Semiconductor-on-insulator constructions

Semiconductor-on-insulator constructions

Fully-depleted castellated gate MOSFET device and method of manufacture thereof

Semiconductor fabrication and structure for field-effect and bipolar transistor devices

Double gate field effect transistor and method of manufacturing the same

Deposition of silicon germanium on silicon-on-insulator structures and bulk substrates

Method and structure for improved MOSFETs using poly/silicide gate height control

Solution to thermal budget

Ultra thin channel MOSFET

METHOD TO PRODUCE TRANSISTOR HAVING REDUCED GATE HEIGHT

Methods of forming devices, constructions and systems comprising thyristors

Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator with hybrid crystal orientations

Bipolar/thin film SOI CMOS structure and method of making same

Computer systems containing resistors which include doped silicon/germanium

Semiconductor device including first and second transistor groups and semiconductor integrated circuit device

Semiconductor device having epitaxial layer

Heterojunction bipolar transistor with monolithically integrated junction field effect transistor and method of manufacturing same

Semiconductor device having electrical contact from opposite sides including a via with an end formed at a bottom surface of the diffusion region

Semiconductor device

Semiconductor device having silicon on insulator structure and method of fabricating the same

Silicon on insulator device and layout method of the same

Integrated semiconductor storage with at least a storage cell and procedure

CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture

SOI type MOSFET

Stress inducing spacers

Semiconductor memory device and method for fabricating the same

Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates

Method of manufacturing semiconductor device having trench isolation

Semiconductor diode with reduced leakage

Localized biasing for silicon on insulator structures

Fabrication method of semiconductor device

Strained Si/SiGe/SOI islands and processes of making same

Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions

Method and structure for buried circuits and devices

Silicon-on-insulator device structure

Method and apparatus for providing an integrated active region on silicon-on-insulator devices

Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction

Method using quasi-planar double gated fin field effect transistor process for the fabrication of a thyristor-based static read/write random-access memory

Vertical system integration

Stabilization in device characteristics of a bipolar transistor that is included in a semiconductor device with a CMOSFET

Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors

Stable PD-SOI devices and methods

Ultra-thin semiconductors bonded on glass substrates

Semiconductor device and method for manufacturing partial SOI substrates

Electronic systems comprising memory devices

Stable PD-SOI devices and methods

Strained semiconductor by wafer bonding with misorientation

Semiconductor device and manufacturing method thereof

Fabrication of silicon-on-nothing (SON) MOSFET fabrication using selective etching of SiGelayer

SOI device with reduced drain induced barrier lowering

Semiconductor chip having multiple functional blocks integrated in a single chip and method for fabricating the same

Method for manufacturing thin film transistor array panel

FET channel having a strained lattice structure along multiple surfaces

Field effect transistor and method of manufacturing the same

Semiconductor element, semiconductor device and methods for manufacturing thereof

Capacitor that includes high permittivity capacitor dielectric

CaF2 lenses with reduced birefringence

Method for fabricating semiconductor device

Coiled circuit device and method of making the same

Semiconductor device

Damascene gate multi-mesa MOSFET

Semiconductor switching devices

Silicon-on-insulator (SOI) integrated circuit (IC) chip with the silicon layers consisting of regions of different thickness

Method for making a system for selecting one wire from a plurality of wires

SRAM cell

Methods of fabricating double-sided hemispherical silicon grain electrodes and capacitor modules

Method and system for fabrication of integrated tunable/switchable passive microwave and millimeter wave modules

Structure and method to fabricate ultra-thin Si channel devices

Multi-configurable independently multi-gated MOSFET

Integrated circuit having pairs of parallel complementary FinFETs

Thin film memory, array, and operation method and manufacture method therefor

Semiconductor memory device including an SOI substrate

High-performance one-transistor memory cell

Double-gated transistor circuit

Method of fabricating semiconductor side wall fin

Methods for producing a 3D semiconductor memory device and structure

3D semiconductor device and structure with transistors

3D semiconductor device and structure with oxide bonds

Monolithic multi-FETs

Integrated circuit with active region jogs

Structure with polycrystalline isolation region below polycrystalline fill shape(s) and selective active device(s), and related method

High density IC capacitor structure

Simplified bias scheme for digital designs

Method for preparing semiconductor capacitor structure

Method of forming high-voltage silicon-on-insulator device with diode connection to handle layer

Devices with slotted active regions

Vertically stacked transistors

Formation of stacked nanosheet semiconductor devices

Formation of semiconductor devices with dual trench isolations

Bulk substrates with a self-aligned buried polycrystalline layer

Method and apparatus for using back gate biasing for power amplifiers for millimeter wave devices

Stacked vertical NFET and PFET

Three-dimensional monolithic vertical field effect transistor logic gates

Fabricating contacts of a CMOS structure

Transistor with improved channel mobility

Semiconductor device and manufacturing method thereof

Devices and methods for fully depleted silicon-on-insulator back biasing

Fully depleted silicon on insulator integration

Method to fabricate both FD-SOI and PD-SOI devices within a single integrated circuit

Methods for forming isolation blocks of semiconductor devices, semiconductor devices and methods for manufacturing the same

Semiconductor device comprising trench isolation

Three-dimensional stacked junctionless channels for dense SRAM

Connection arrangements for integrated lateral diffusion field effect transistors

Sidewall spacer for integration of group III nitride with patterned silicon substrate

Fabricating contacts of a CMOS structure

Semiconductor device including buried capacitive structures and a method of forming the same

Diffusion break forming after source/drain forming and related IC structure

SRAM bitcell structures facilitating biasing of pull-down transistors

SRAM bitcell structures facilitating biasing of pull-up transistors

Fully depleted silicon-on-insulator (FDSOI) transistor device and self-aligned active area in FDSOI bulk exposed regions

Systems, methods and apparatus for enabling high voltage circuits

Contact punch through mitigation in SOI substrate

Semiconductor structure including a first transistor at a semiconductor-on-insulator region and a second transistor at a bulk region and method for the formation thereof

Body tie optimization for stacked transistor amplifier

Conductive contacts in semiconductor on insulator substrate

Methods of forming a device having semiconductor devices on two sides of a buried dielectric layer

Lateral bipolar junction transistor with multiple base lengths

Method of making thermally-isolated silicon-based integrated circuits

Method for local thinning of top silicon layer of SOI wafer

Electronic chip comprising transistors with front and back gates

On-chip DC-DC power converters with fully integrated GaN power switches, silicon CMOS transistors and magnetic inductors

Defect reduction in channel silicon germanium on patterned silicon

Integrated circuit including a dummy gate structure and method for the formation thereof

Hybrid integration fabrication of nanowire gate-all-around GE PFET and polygonal III-V PFET CMOS device

Semiconductor on insulator (SOI) block with a guard ring

Grounded die seal integrated circuit structure for RF circuits

Pass-through contact using silicide

Methods for fabricating integrated circuits with low, medium, and/or high voltage transistors on an extremely thin silicon-on-insulator substrate

Semiconductor structure including a trench capping layer and method for the formation thereof

Reduced parasitic capacitance and contact resistance in extremely thin silicon-on-insulator (ETSOI) devices due to wrap-around structure of source/drain regions

Chip structures with distributed wiring

Fabrication of semiconductor structures

Self-aligned contacts for vertical field effect transistors

Fabrication of hybrid semiconductor circuits

Subsurface wires of integrated chip and methods of forming

CMOS structures with selective tensile strained NFET fins and relaxed PFET fins

Method of fabrication of ETSOI CMOS device by sidewall image transfer (SIT)

Stacked nanowire semiconductor device

Connecting to back-plate contacts or diode junctions through a RMG electrode and resulting devices

Method and structure for forming dually strained silicon

Complementary SOI lateral bipolar transistors with backplate bias

Method for creating metal gate resistor in FDSOL and resulting device

Method of fabricating a semiconductor device

Highly scaled tunnel FET with tight pitch and method to fabricate same

Self-aligned contacts for vertical field effect transistors

Biodegradable microwave electronic devices

Optoelectronics and CMOS integration on GOI substrate

Preventing unauthorized use of integrated circuits for radiation-hard applications

Method for integrating thin-film transistors on an isolation region in an integrated circuit and resulting device

Fabrication of a deep trench memory cell

Efficient buried oxide layer interconnect scheme

Complementary metal-oxide silicon having silicon and silicon germanium channels

Multiple Vin III-V FETs

Method for fabricating semiconductor layers including transistor channels having different strain states, and related semiconductor layers

Monolithic integration of GaN and InP components

Semiconductor on polymer substrate

Integrated monolithic galvanic isolator