Method and structure for forming dually strained silicon

Description

BACKGROUND

The present invention is directed toward semiconductor structures, and more particularly to forming a dually strained silicon structure with different dielectric materials underneath the silicon.

Strain engineering is critical for improving complementary metal-oxide semiconductor (CMOS) performance. With continued downscaling of devices, the conventional external stress techniques (e.g., stress liners) run out of steam due to the diminishing spacing for incorporating those external stressors. Thus, as technology advances, channel strain becomes increasingly important.

Young's modulus, also known as the elastic modulus, defines the relationship between stress (force per unit area) and strain (proportional deformation) in a material. Specifically, Young's modulus is the ratio of the stress (force per unit area) along an axis to the strain (ratio of deformation over initial length) along that axis in the range of stress in which Hooke's law holds.

BRIEF SUMMARY

Aspects of the present invention include methods and structures for forming dually strained CMOS (tensile Si NFET and compressive SiGe PFET) by bonding initially compressive strain SiGe on pre-patterned dielectric materials on base wafer. The SiGe is bonded on a “soft” dielectric in an NFET region so it elastically relaxes. In a PFET region, the SiGe is bonded to a rigid dielectric so it remains compressively strained. Tensile Si is then epitaxially grown on the relaxed SiGe. The process results in a unique structure of tensile Si on relaxed SiGe on soft dielectric for NFET and compressive SiGe on rigid dielectric for PFET.

One example aspect of the present invention is a semiconductor structure. The semiconductor structure includes a monolithic substrate, a first dielectric layer carried by the monolithic substrate and a second dielectric layer carried by the monolithic substrate. The first dielectric layer has a first Young's modulus, and the second dielectric layer has a second Young's modulus. The first Young's modulus is at least twice the second Young's modulus. A compressive SiGe layer is positioned over and in contact with the first dielectric layer. A relaxed SiGe layer is positioned over and in contact with the second dielectric layer. The relaxed SiGe layer is spaced apart from the compressive SiGe layer.

Another example aspect of the present invention is a method for fabricating a semiconductor structure. The method includes depositing a first dielectric layer with a first Young's modulus over a substrate. Another depositing step deposits a second dielectric layer with a second Young's modulus over the monolithic substrate lateral to the first dielectric layer. The first Young's modulus is at least twice the second Young's modulus. A bonding step bonds a compressed SiGe layer to the first dielectric layer and the second dielectric layer. An annealing step anneals the semiconductor structure such that a first region of the SiGe layer over the first dielectric layer remains the compressed SiGe layer and a second region of the SiGe layer over the second dielectric layer forms a relaxed SiGe layer.

A further example aspect of the present invention is a method for fabricating a semiconductor structure. The method is depositing a first dielectric layer with a first Young's modulus over a substrate. Another depositing step deposits a second dielectric layer with a second Young's modulus over the monolithic substrate lateral to the first dielectric layer. The second Young's modulus is a least twice the first Young's modulus. A bonding step bonds a compressed SiGe layer to the first dielectric layer and the second dielectric layer. An annealing step anneals the semiconductor structure such that a first region of the SiGe layer over the first dielectric layer forms a relaxed SiGe layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 shows an example semiconductor structure contemplated by the present invention.

FIG. 2 shows a fabrication step of depositing a first dielectric layer with a first Young's modulus over a substrate.

FIG. 3 shows a fabrication step of patterning the first dielectric layer using a hardmask.

FIG. 4 shows the fabrication steps of removing the hardmask and depositing a second dielectric layer with a second Young's modulus over the monolithic substrate lateral to the first dielectric layer.

FIG. 5 shows a fabrication step of planarizing the first dielectric layer and the second dielectric layer.

FIG. 6 shows a fabrication step of bonding a compressed SiGe layer to the first dielectric layer and the second dielectric layer.

FIG. 7 shows a fabrication step of removing the donor Si substrate from the bonded wafer.

FIG. 8 shows a fabrication step of etching the SiGe layer so that a first region of the SiGe layer over the first dielectric layer is spaced apart from the second region of the SiGe layer over the second dielectric layer by a separation region.

FIG. 9 shows a fabrication step of annealing the semiconductor structure such that the first region of the SiGe layer over the first dielectric layer remains the compressed SiGe layer and the second region of the SiGe layer over the second dielectric layer forms a relaxed SiGe layer.

FIG. 10 shows a fabrication step of depositing a dielectric material in the separation region.

DETAILED DESCRIPTION

The present invention is described with reference to embodiments of the invention. Throughout the description of the invention reference is made to FIGS. 1-10. When referring to the figures, like structures and elements shown throughout are indicated with like reference numerals.

FIG. 1 shows an example semiconductor structure 102 contemplated by the present invention. The semiconductor structure 102 includes a monolithic substrate 104, such as crystalline Si.

A first dielectric layer 106 with a first Young's modulus is carried by the substrate 104. A second dielectric layer 108 with a second Young's modulus is carried by the monolithic substrate 104 and is positioned lateral to the first dielectric layer 106. Furthermore, the first Young's modulus is at least twice the second Young's modulus. In one embodiment, the first Young's modulus is greater than 200 GPa and the second Young's modulus is less than 100 GPa. The first dielectric layer 106 may be composed of a different material than the second dielectric layer 108. For example, the first dielectric layer 106 may be a nitride material, such as silicon nitride (Si₃N₄), and the second dielectric layer 108 may be an oxide material, such as borophosphosilicate glass (BPSG).

A compressive SiGe layer 110 is positioned over and in contact with the first dielectric layer 106. Compressive straining of SiGe can improve hole mobility within the SiGe. A relaxed SiGe layer 112 is positioned over and in contact with the second dielectric layer 108.

The relaxed SiGe layer 112 is spaced apart from the compressive SiGe layer 110 by a dielectric divider 114 positioned between the relaxed SiGe layer 112 and the compressive SiGe layer 110. It is contemplated that first dielectric layer 106 and the second dielectric layer 108 may also be spaced apart by the dielectric divider 114. In one embodiment, the dielectric divider 114 is SiO₂.

The semiconductor structure 102 includes a tensile Si layer 116 positioned over and in contact with the relaxed SiGe layer 112. Tensile straining of Si can improve electron mobility. The tensile Si layer 116 is also spaced apart from the compressive SiGe layer 110 by the dielectric divider 114.

The semiconductor structure 102 may include a lateral, n-channel field-effect transistor (NFET) 118 at the tensile Si layer 116, and a lateral, p-channel field-effect transistor (PFET) 120 at the compressive SiGe layer 110. Specifically, the NFET 118 includes an n-doped source 122, gate 124 and n-doped drain 126. Similarly, the PFET includes a p-doped source 128, gate 130 and p-doped drain 132. It is contemplated that in other embodiments of the present invention the Si layer 116 and/or SiGe layer 110 can be used to form multigate devices, such as FinFETs.

Since the NFET 118 is fabricated on tensile Si, its performance is enhanced by greater electron mobility at its channel. Since the PFET 120 is fabricated on compressive SiGe, its performance is enhanced by greater hole mobility at its channel. Thus, the semiconductor structure 102 can include dually strained CMOS (tensile Si NFET and compressive SiGe PFET).

Another embodiment of the present invention is a method for fabricating a semiconductor structure, as illustrated in FIGS. 2-10. FIG. 2 shows a fabrication step of depositing a first dielectric layer 204 with a first Young's modulus over a substrate 202. In one embodiment, the first Young's modulus is greater than 200 GPa. The first dielectric layer 204 may be a nitride material, such as silicon nitride (Si₃N₄).

FIG. 3 shows a fabrication step of patterning the first dielectric layer 204 using a hardmask 302. This step may be achieved using, for example, reactive ion etching (RIE).

FIG. 4 shows the fabrication steps of removing the hardmask 302 and depositing a second dielectric layer 402 with a second Young's modulus over the monolithic substrate 202 lateral to the first dielectric layer. In one embodiment, the first Young's modulus is at least twice the second Young's modulus. In a particular embodiment, the second Young's modulus is less than 100 GPa. The second dielectric layer 402 may be composed of a different material than the first dielectric layer 204. In one embodiment, the second dielectric layer 402 is an oxide material, such as borophosphosilicate glass (BPSG).

FIG. 5 shows a fabrication step of planarizing the first dielectric layer 204 and the second dielectric layer 402. This step may be achieved using, for example, chemical mechanical planarization (CMP). Those skilled in the art will appreciate that the order in which the dielectric layers 204 and 402 are deposited may be reversed. For example, the fabrication process may include depositing a soft oxide layer (e.g., Young's modulus less than 100 GPa) then depositing a rigid nitride layer (e.g., Young's modulus greater than 200 GPa).

FIG. 6 shows a fabrication step of bonding a compressed SiGe layer 602 to the first dielectric layer 204 and the second dielectric layer 402. During this operation, a donor wafer 604 is prepared by epitaxially growing SiGe on the donor Si substrate 606. The donor wafer 604 is then directly bonded to the base wafer 608.

FIG. 7 shows a fabrication step of removing the donor Si substrate 606 from the bonded wafer. This step can include CMP followed by a chemical etch to accurately adjust the thickness of the remaining compressed SiGe layer 602.

FIG. 8 shows a fabrication step of etching the SiGe layer 602 so that a first region 802 of the SiGe layer 602 over the first dielectric layer 602 is spaced apart from the second region 804 of the SiGe layer 602 over the second dielectric layer 402 by a separation region 806. The separation region 806 may be etched through the first dielectric layer 204 and the second dielectric layer 402 and stopping at the substrate 202. Alternatively, as shown in FIG. 1, the separation region 806 may stop at the first dielectric layer 204 and the second dielectric layer 402.

FIG. 9 shows a fabrication step of annealing the semiconductor structure such that the first region 802 of the SiGe layer over the first dielectric layer 204 remains the compressed SiGe layer 602 and the second region 804 of the SiGe layer over the second dielectric layer 402 forms a relaxed SiGe layer 902.

FIG. 10 shows a fabrication step of depositing a dielectric material 1002 in the separation region. In one embodiment, the dielectric material 1002 is SiO₂. The figure also shows a fabrication step of growing an epitaxial Si layer over the relaxed SiGe layer 902 to form a tensile Si layer 1004 in contact with the relaxed SiGe 902. This step may include etching the relaxed SiGe 902 before growing the epitaxial Si layer.

Returning to FIG. 1, the fabrication process may include forming an n-channel field-effect transistor (NFET) at the tensile Si layer, and forming a p-channel field-effect transistor (PFET) at the compressive SiGe layer. Thus, a dually strained CMOS structure (tensile Si NFET and compressive SiGe PFET) is formed.

The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.