Method and system for a photonic interposer

Method for late differential SOI thinning for improved FDSOI performance and HCI optimization

SEMICONDUCTOR DEVICES INCLUDING TRAP RICH LAYER REGIONS

3D IC semiconductor device and structure with stacked memory

Extremely thin silicon-on-insulator silicon germanium device without edge strain relaxation

SEMICONDUCTOR DEVICE

Method of making thin SRAM cell having vertical transistors

Copper interconnect for improving radio frequency (RF) silicon-on-insulator (SOI) switch field effect transistor (FET) stacks

Semi-sequential 3D integration

POROUS SEMICONDUCTOR LAYER TRANSFER FOR AN INTEGRATED CIRCUIT STRUCTURE

Double balanced mixer

Semiconductor device structure with self-aligned capacitor device

Substrate contact land for an MOS transistor in an SOI substrate, in particular an FDSOI substrate

Semiconductor devices on two sides of an isolation layer

Semiconductor structure and related method

Display driving circuit, array substrate, circuit driving method, and display device

Pixel structure and manufacturing method thereof, array substrate and display apparatus

NVM device in SOI technology and method of fabricating an according device

System on chip fully-depleted silicon on insulator with RF and MM-wave integrated functions

System on chip fully-depleted silicon on insulator with rf and mm-wave integrated functions

RADIO-FREQUENCY SWITCH WITHOUT NEGATIVE VOLTAGES

Lateral bipolar junction transistor with multiple base lengths

Semiconductor device

Air gap spacer implant for NZG reliability fix

Semiconductor device and manufacturing method thereof

Polycrystalline ceramic substrate and method of manufacture

Packaging optoelectronic components and CMOS circuitry using silicon-on-insulator substrates for photonics applications

Systems and methods for in vivo detection of electrophysiological and electrochemical signals

On-chip DC-DC power converters with fully integrated GaN power switches, silicon CMOS transistors and magnetic inductors

Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor

Manufacturing method of semiconductor device and semiconductor device

Stacked nanowire device width adjustment by gas cluster ion beam (GCIB)

Semiconductor device and monolithic semiconductor device including a power semiconductor device and a control circuit

Circuits and methods including dual gate field effect transistors

Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dial raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI

Anti-fuse with reduced programming voltage

Trap layer substrate stacking technique to improve performance for RF devices

Method of making a fully depleted semiconductor-on-insulator programmable cell and structure thereof

Semiconductor memory device including multilayer wiring layer

Systems and methods for thermal conduction using S-contacts

Reduced substrate effects in monolithically integrated RF circuits

Semiconductor memory having both volatile and non-volatile functionality and method of operating

Display device and method of manufacturing the same

Integrated circuits with capacitors and methods for producing the same

Method for manufacturing semiconductor device

Method of forming a semiconductor device having a dopant in the substrate adjacent the insulator

Semiconductor device

Creation of wide band gap material for integration to SOI thereof

Methods for forming hybrid vertical transistors

Integrated circuits with capacitors and methods for producing the same

Method for producing on the same transistors substrate having different characteristics

Method of manufacturing semiconductor device

Double sided NMOS/PMOS structure and methods of forming the same

Method to form strained channel in thin box SOI structures by elastic strain relaxation of the substrate

Methods for forming integrated circuits that include a dummy gate structure

High density programmable e-fuse co-integrated with vertical FETs

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Method for the formation of transistors PDSO1 and FDSO1 on a same substrate

HIGH-VOLTAGE TRANSISTOR DEVICE

Passive components implemented on a plurality of stacked insulators

S-contact for SOI

Method for producing on the same transistors substrate having different characteristics

Semiconductor structure with integrated passive structures

GATE PROTECTION FOR HV-STRESS APPLICATION

Nanofluid sensor with real-time spatial sensing

Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI

Semiconductor on insulator (SOI) block with a guard ring

Integrated circuits with deep and ultra shallow trench isolations and methods for fabricating the same

Prevention of charging damage in full-depletion devices

Prevention of charging damage in full-depletion devices

Air gap over transistor gate and related method

Method, apparatus and system for back gate biasing for FD-SOI devices

SOI WAFERS AND DEVICES WITH BURIED STRESSOR

Group III-N transistor on nanoscale template structures

Semiconductor film with adhesion layer and method for forming the same

CMOS compatible BioFET

Leakage-free implantation-free ETSOI transistors

FDSOI-capacitor

Integrated circuits with selectively strained device regions and methods for fabricating same

Commonly-bodied field-effect transistors

Method and structure providing optical isolation of a waveguide on a silicon-on-insulator substrate

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Tunable capacitor for FDSOI applications

Systems and Methods for a Semiconductor Structure Having Multiple Semiconductor-Device Layers

Semiconductor device and fabricating the same

Switchable die seal connection

Flipped vertical field-effect-transistor

Manufacturing of silicon strained in tension on insulator by amorphisation then recrystallisation

Stretchable broad impedance bandwidth RFID devices

Frameless display device with concealed drive circuit board and manufacturing method thereof

Semiconductor device with silicon layer containing carbon

Method of manufacturing a MOSFET on an SOI substrate

Peeling method and manufacturing method of flexible device

Method for forming an electrical contact between a semiconductor film and a bulk handle wafer, and resulting structure

Fabrication of semiconductor structures

Double balanced mixer

Enhanced substrate contact for MOS transistor in an SOI substrate, in particular an FDSOI substrate

Aluminum nitride based Silicon-on-Insulator substrate structure

VARIABLE BURIED OXIDE THICKNESS FOR SILICON-ON-INSULATOR DEVICES

Semiconductor device and manufacturing method thereof

Multi-finger devices in mutliple-gate-contacted-pitch, integrated structures

Semiconductor structure including a transistor including a gate electrode region provided in a substrate and method for the formation thereof

VARIABLE HANDLE WAFER RESISTIVITY FOR SILICON-ON-INSULATOR DEVICES

Semiconductor device and manufacturing method thereof

Method for reduced parasitic capacitance and contact resistance in extremely thin silicon-on-insulator (ETSOI) devices due to wrap-around structure of source/drain regions

Method of forming MOS and bipolar transistors

Inline monitoring of transistor-to-transistor critical dimension

Semiconductor device

Methods for varied strain on nano-scale field effect transistor devices

FDSOI with on-chip physically unclonable function

Semiconductor device and manufacturing method thereof

Voltage-controlled oscillator

SOI substrate and manufacturing method thereof

Field-effect transistors with a non-relaxed strained channel

SOI SUBSTRATE AND MANUFACTURING METHOD THEREOF

Memory device and semiconductor device

Array substrate for display device and manufacturing method thereof

Transistor layout with low aspect ratio

METHOD FOR MANUFACTURING A TRANSISTOR HAVING A SHARP JUNCTION BY FORMING RAISED SOURCE-DRAIN REGIONS BEFORE FORMING GATE REGIONS AND CORRESPONDING TRANSISTOR PRODUCED BY SAID METHOD

Silicon controlled rectifier (SCR) based ESD protection device

Via self alignment and shorting improvement with airgap integration capacitance benefit

Semiconductor device and method of manufacturing same

Vertical semiconductor device with thinned substrate

Methods of forming field effect transistor (FET) and non-FET circuit elements on a semiconductor-on-insulator substrate

ESD protection device with buried layer having variable doping concentrations

Rapid heating process in the production of semiconductor components

Stacked nanowire devices

Semiconductor device including a high-electron-mobility transistor (HEMT) and method for manufacturing the same

Third type of metal gate stack for CMOS devices

Method and structure for forming on-chip anti-fuse with reduced breakdown voltage

Semiconductor structure and fabrication method thereof

Hybrid ETSOI structure to minimize noise coupling from TSV

Fabricating a dual gate stack of a CMOS structure

Method for forming a semiconductor structure containing high mobility semiconductor channel materials

Semiconductor device, semiconductor wafer, module, electronic device, and manufacturing method thereof

Manufacturing method of semiconductor device and semiconductor device

Method for forming a semiconductor structure containing high mobility semiconductor channel materials

3D semiconductor device and system

Method of localized modification of the stresses in a substrate of the SOI type, in particular FD SOI type, and corresponding device

Semiconductor device and manufacturing method thereof

Method for manufacturing semiconductor structure

Incremental multi-patterning validation

Monolithic integration of antenna switch and diplexer

Switching system and method

Semiconductor structure including a first transistor and a second transistor

Semiconductor device and fabricating method thereof

Method of manufacturing SOI wafer

Semiconductor-metal-on-insulator structures, methods of forming such structures, and semiconductor devices including such structures

Stress memorization technique for strain coupling enhancement in bulk finFET device

Controlled confined lateral III-V epitaxy

FinFET with stacked faceted S/D epitaxy for improved contact resistance

3D semiconductor memory device and structure

Packaging optoelectronic components and CMOS circuitry using silicon-on-insulator substrates for photonics applications

Packaging optoelectronic components and CMOS circuitry using silicon-on-insulator substrates for photonics applications

Method of manufacturing semiconductor device reducing variation in thickness of silicon layer among semiconductor wafers

Leakage-free implantation-free ETSOI transistors

Method to form strained nFET and strained pFET nanowires on a same substrate

Junction butting structure using nonuniform trench shape

ULTRASOUND T/R ISOLTATION DISOLATOR WITH FAST RECOVERY TIME ON SOI

Structure and method for fully depleted silicon on insulator structure for threshold voltage modification

Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon region

Extremely thin silicon-on-insulator silicon germanium device without edge strain relaxation

Channel silicon germanium formation method

S-contact for SOI

TRENCH BASED CHARGE PUMP DEVICE

Semiconductor nanowire device and fabrication method thereof

Semiconductor Devices Having Insulating Substrates and Methods of Formation Thereof

Array substrate and method of manufacturing the same, and display apparatus

Optoelectronics and CMOS integration on GOI substrate

Semiconductor device and method for manufacturing the same

Semiconductor integrated circuit

Method for producing one-time-programmable memory cells and corresponding integrated circuit

CMOS nanowire structure

Substrate having two semiconductor materials on insulator

Electronic devices and systems, and methods for making and using the same

Semiconductor device, manufacturing method thereof, and electronic device

Method of manufacturing a device with MOS transistors

Semiconductor device and fabrication method thereof

System on chip material co-integration

Methods of forming strained-semiconductor-on-insulator device structures

Semiconductor on insulator substrate with back bias

Complementary SOI lateral bipolar transistors with backplate bias

Trap layer substrate stacking technique to improve performance for RF devices

Radio-frequency isolation using front side opening

Co-fabricated bulk devices and semiconductor-on-insulator devices

Contacting SOI subsrates

Method of making embedded memory device with silicon-on-insulator substrate

Integrated circuits (ICs) on a glass substrate

Semiconductor device including a repeater/buffer at higher metal routing layers and methods of manufacturing the same

Stacked nanowire device width adjustment by gas cluster ion beam (GCIB)

Highly scaled tunnel FET with tight pitch and method to fabricate same

Stacked nanowire device width adjustment by gas cluster ion beam (GCIB)

Semiconductor device with reduced poly spacing effect

Integrated circuits (ICS) on a glass substrate

Dual-semiconductor complementary metal-oxide-semiconductor device

Highly scaled tunnel FET with tight pitch and method to fabricate same

Composite substrate

Integrated circuit composed of tunnel field-effect transistors and method for manufacturing same

Method of fabricating a transistor channel structure with uniaxial strain

Removal of semiconductor growth defects

Method for causing tensile strain in a semiconductor film

Method for manufacturing a transistor having a sharp junction by forming raised source-drain regions before forming gate regions and corresponding transistor produced by said method

Method of forming a semiconductor device with STI structures on an SOI substrate

Techniques for dual dielectric thickness for a nanowire CMOS technology using oxygen growth

Raised e-fuse

Silicon on porous silicon

SOI wafer manufacturing process and SOI wafer

Transisitor comprising oxide semiconductor

Double-side process silicon MOS and passive devices for RF front-end modules

Semiconductor Device With Self-Aligned Back Side Features

Packaging optoelectronic components and CMOS circuitry using silicon-on-insulator substrates for photonics applications

Method and structure for forming on-chip anti-fuse with reduced breakdown voltage

Method of forming semiconductor device

Capacitor structure and method of forming a capacitor structure

Semiconductor device and method of fabricating the same

Semiconductor device and manufacturing method of the same

III-V, SiGe, or Ge base lateral bipolar transistor and CMOS hybrid technology

Memory device, semiconductor device, and electronic device

Hybrid computing module

Hybrid computing module

Hybrid computing module

Semiconductor memory having both volatile and non-volatile functionality

Method including a formation of a transistor and semiconductor structure including a first transistor and a second transistor

Semiconductor structures with deep trench capacitor and methods of manufacture

CMOS compatible BioFET

Method of manufacturing a semiconductor device to prevent occurrence of short-channel characteristics and parasitic capacitance

Liquid crystal display device and electronic device

SOI-based semiconductor device with dynamic threshold voltage

Semiconductor device and fabricating method thereof

Substrate contact land for an MOS transistor in an SOI substrate, in particular an FDSOI substrate

Interconnect structures and fabrication method thereof

Creation of wide band gap material for integration to SOI thereof

Structure and method for adjusting threshold voltage of the array of transistors

FDSOI voltage reference

Systems and methods for a semiconductor structure having multiple semiconductor-device layers

Tunable capacitor for FDSOI applications

Semiconductor device having recessed edges and method of manufacture

METHOD AND APPARATUS FOR HIGH PERFORMANCE PASSIVE-ACTIVE CIRCUIT INTEGRATION

Isolated semiconductor layer over buried isolation layer

Dual channel memory

Process for producing a contact on an active zone of an integrated circuit, for example produced on an SOI substrate, in particular an FDSOI substrate, and corresponding integrated circuit

Semiconductor device and method for controlling semiconductor device

Fully-depleted silicon-on-insulator transistors

Method for manufacturing a high-resistivity semiconductor-on-insulator substrate including an RF circuit overlapping a doped region in the substrate

Semiconductor device and radio frequency module formed on high resistivity substrate

LOW-WARPAGE SEMICONDUCTOR SUBSTRATE AND METHOD FOR PREPARING SAME

High power RF switches using multiple optimized transistors

Manufacturing of self aligned interconnection elements for 3D integrated circuits

Vertically integrated memory cell

Techniques for multiple gate workfunctions for a nanowire CMOS technology

Semiconductor-on-insulator with back side heat dissipation

Memory device and method for manufacturing the same

Electronic devices and systems, and methods for making and using the same

Bottom-gate thin-body transistors for stacked wafer integrated circuits

P-channel transistor having an increased channel mobility due to a compressive stress-inducing gate electrode

Semiconductor device

Semiconductor structure with an L-shaped bottom

Method for local isolation between transistors produced on an SOI substrate, in particular an FDSOI substrate, and corresponding integrated circuit

Transistor with a low-k sidewall spacer and method of making same

Embedded carbon-doped germanium as stressor for germanium nFET devices

Semiconductor device and structure

Array substrate, method for manufacturing the same, and display apparatus

E-fuse in SOI configuration

Display device including auxiliary lines and polarizing films, and manufacturing method thereof

Radio frequency isolation using substrate opening

Radio frequency isolation cavity formation using sacrificial material

Channel SiGe devices with multiple threshold voltages on hybrid oriented substrates, and methods of manufacturing same

SILICON-ON-INSULATOR DEVICES HAVING CONTACT LAYER

Cavity formation in semiconductor devices

Backside cavity formation in semiconductor devices

Cavity formation in interface layer in semiconductor devices

SUBSTRATE BIAS FOR FIELD-EFFECT TRANSISTOR DEVICES

Semiconductor structure having logic region and analog region

Preventing unauthorized use of integrated circuits for radiation-hard applications

Method of manufacturing P-channel FET device with SiGe channel

Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer

Wide band gap transistors on non-native semiconductor substrates and methods of manufacture thereof

Integrated circuit product with bulk and SOI semiconductor devices

Semiconductor structure with integrated passive structures

Semiconductor structure with an L-shaped bottom plate

Process for fabricating SOI transistors for an increased integration density

Semiconductor structure with integrated passive structures

Semiconductor structure with an L-shaped bottom plate

Devices having multiple threshold voltages and method of fabricating such devices

Semiconductor device structures and methods of forming semiconductor structures

Semiconductor device structure useful for bulk transistor and method of manufacturing same where a substrate extends commonly over a transistor, an element region, and a separation region

Method for making strained semiconductor device and related methods

SILICON-ON-INSULATOR (SOI) WAFERS EMPLOYING MOLDED SUBSTRATES TO IMPROVE INSULATION AND REDUCE CURRENT LEAKAGE

Semiconductor devices having insulating substrates and methods of formation thereof

Techniques for multiple gate workfunctions for a nanowire CMOS technology

METHOD OF FORMATION OF A SUBSTRATE OF THE SOI, IN PARTICULAR THE FDSOI, TYPE ADAPTED TO TRANSISTORS HAVING GATE DIELECTRICS OF DIFFERENT THICKNESSES, CORRESPONDING SUBSTRATE AND INTEGRATED CIRCUIT

Efficient buried oxide layer interconnect scheme

Techniques for dual dielectric thickness for a nanowire CMOS technology using oxygen growth

Method and system for photonic interposer

Optoelectronics and CMOS integration on GOI substrate

Integrated circuits using silicon on insulator substrates and methods of manufacturing the same

Method of making a CMOS semiconductor device using a stressed silicon-on-insulator (SOI) wafer

Semiconductor structure including backgate regions and method for the formation thereof

Semiconductor device and method for fabricating the same

Structure for integration of an III-V compound semiconductor on SOI