207547 ⎘
Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof; Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof; Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
Channel semiconductor alloy layer growth adjusted by impurity ion implantation
#1502Transistor having a stressed body
#1503Carbon-doped cap for a raised active semiconductor region
#1504Semiconductor arrangement with active drift zone
#1505Thin body switch transistor
#1506System with memory having voltage applying unit
#1507Selective amorphization for signal isolation and linearity
#1508Methods for the formation of a trap rich layer
#1509Reliable electrical fuse with localized programming and method of making the same
#1510Semiconductor device and manufacturing method thereof
#1511Method and system for a photonic interposer
#1512Semiconductor device
#1513Structure and method for adjusting threshold voltage of the array of transistors
#1514Device including a transistor having a stressed channel region and method for the formation thereof
#1515Method for manufacturing semiconductor device
#1516Semiconductor memory having both volatile and non-volatile functionality and method of operating
#1517Bipolar transistor, band-gap reference circuit and virtual ground reference circuit
#1518Semiconductor device and method of manufacturing the same
#1519Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon-germanium region
#1520Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon region
#1521Method for producing a silicon-germanium film with variable germanium content
#1522Method for manufacturing silicon-based electronics with disabling feature
#1523Silicon-based electronics with disabling feature
#1524Forming semiconductor structure with device layers and TRL
#1525Method of fabricating a semiconductor device including embedded crystalline back-gate bias planes
#1526Semiconductor-on-insulator integrated circuit with back side gate
#1527Semiconductor device
#1528Fabricating polysilicon MOS devices and passive ESD devices
#1529Memory with carbon-containing silicon channel
#1530Integrated circuit having raised source drains devices with reduced silicide contact resistance and methods to fabricate same
#1531Structure and method for reducing floating body effect of SOI MOSFETS
#1532Recessed gate silicon-on-insulator floating body device with self-aligned lateral isolation
#1533Semiconductor device and method of manufacturing same
#1534SOI substrate, method for manufacturing the same, and semiconductor device
#1535Semiconductor device and driving method thereof
#1536Semiconductor device including multilayer wiring layer
#1537Semiconductor-on-insulator integrated circuit with reduced off-state capacitance
#1538Redistribution layer contacting first wafer through second wafer
#1539Semiconductor device and electronic device having the same
#1540SEMICONDUCTOR-ON-INSULATOR STRUCTURE AND PROCESS FOR PRODUCING SAME
#15416T SRAM architecture for gate-all-around nanowire devices
#15426T SRAM architecture for gate-all-around nanowire devices
#1543Method of producing a silicon-on-insulator article
#1544Simplified multi-threshold voltage scheme for fully depleted SOI MOSFETs
#1545Semiconductor memory device
#1546Replacement gate integration scheme employing multiple types of disposable gate structures
#1547Method of semiconductor device including step of cutting substrate at opening of insulating layer
#1548Contact isolation scheme for thin buried oxide substrate devices
#1549Methods for antenna switch modules
#1550Semiconductor device and method for manufacturing semiconductor device
#1551Semiconductor-on-insulator integrated circuit with interconnect below the insulator
#1552Thermally assisted flash memory with diode strapping
#1553Method of forming a strained silicon layer
#1554Integrated passive devices for FinFET technologies
#1555Circuit structures, memory circuitry, and methods
#1556Integration of a replica circuit and a transformer above a dielectric substrate
#1557Hybrid ETSOI structure to minimize noise coupling from TSV
#1558Semiconductor structures with deep trench capacitor and methods of manufacture
#1559Carbon-doped cap for a raised active semiconductor region
#1560Three-terminal printed devices interconnected as circuits
#1561Semiconductor structure
#1562Planar polysilicon regions for precision resistors and electrical fuses and method of fabrication
#1563Extremely thin semiconductor on insulator (ETSOI) logic and memory hybrid chip
#1564Monolithic three dimensional integration of semiconductor integrated circuits
#1565Methods of forming strained-semiconductor-on-insulator device structures
#1566SEMICONDUCTOR RADIO FREQUENCY SWITCH WITH BODY CONTACT
#1567Semiconductor memory device and manufacturing method thereof
#1568Electronic device
#1569Wafer support system and method for separating support substrate from solid-phase bonded wafer and method for manufacturing semiconductor device
#1570Method of fabricating isolated capacitors and structure thereof
#1571SOI RF device and method for forming the same
#1572Membrane-based sensor device with non-dielectric etch-stop layer around substrate recess
#1573Convex shaped thin-film transistor device having elongated channel over insulating layer
#1574Memory device
#1575Nanowire capacitor for bidirectional operation
#1576Nanowire capacitor for bidirectional operation
#1577Methods of forming semiconductor structures including bodies of semiconductor material
#1578Semiconductor device and manufacturing method thereof
#1579Semiconductor device with silicon layer containing carbon
#1580Butted SOI junction isolation structures and devices and method of fabrication
#1581Transistor with longitudinal strain in channel induced by buried stressor relaxed by implantation
#1582Array substrate and manufacturing method thereof
#1583Hybrid fin field-effect transistor structures and related methods
#1584Photonics device and CMOS device having a common gate
#1585Fabricating polysilicon MOS devices and passive ESD devices
#1586Integrated circuit having back gating, improved isolation and reduced well resistance and method to fabricate same
#1587Fabrication method of semiconductor apparatus
#1588Integrated circuit comprising a clock tree cell
#1589Integrated circuit comprising a clock tree cell
#1590Silicon-on-insulator radio frequency device and silicon-on-insulator substrate
#1591Method for generating a topography of an FDSOI integrated circuit
#1592Lateral bipolar transistor and CMOS hybrid technology
#1593Electrostatic discharge resistant diodes
#1594Semiconductor devices having insulating substrates and methods of formation thereof
#1595Device with FD-SOI cell and insulated semiconductor contact region and related methods
#1596Memory device, semiconductor device, and electronic device
#1597Method of forming substrate contact for semiconductor on insulator (SOI) substrate
#1598Integrated circuit with a thin body field effect transistor and capacitor
#1599Semiconductor component and methods for producing a semiconductor component
#1600Integrated circuit with a thin body field effect transistor and capacitor
#1601Co-integration of elemental semiconductor devices and compound semiconductor devices
#1602Recessed gate field effect transistor
#1603On-chip diode with fully depleted semiconductor devices
#1604Structure and method to form passive devices in ETSOI process flow
#1605Semiconductor device having diffusion barrier to reduce back channel leakage
#1606Semiconductor structure including a semiconductor-on-insulator region and a bulk region, and method for the formation thereof
#1607Co-integration of elemental semiconductor devices and compound semiconductor devices
#1608Structure and method to improve ETSOI MOSFETS with back gate
#1609Fabrication of reverse shallow trench isolation structures with super-steep retrograde wells
#1610Method for manufacturing bonded substrate having an insulator layer in part of bonded substrate
#1611Self-Aligned Silicide Bottom Plate for EDRAM Applications by Self-Diffusing Metal in CVD/ALD Metal Process
#1612Back-end transistors with highly doped low-temperature contacts
#1613Self-aligned silicide bottom plate for eDRAM applications by self-diffusing metal in CVD/ALD metal process
#1614Back-end transistors with highly doped low-temperature contacts
#1615Dual-gate bio/chem sensor
#1616Extremely thin semiconductor-on-insulator with back gate contact
#1617Extremely thin semiconductor-on-insulator with back gate contact
#1618Silicon device on SI:C-OI and SGOI and method of manufacture
#1619Prevention of contact to substrate shorts
#1620Thin film transistor and fabricating method
#1621Non-volatile memory device employing semiconductor nanoparticles
#1622Method for manufacturing SOI substrate and semiconductor device
#1623Method for producing a field effect transistor with implantation through the spacers
#1624Lateral epitaxial grown SOI in deep trench structures and methods of manufacture
#1625Semiconductor structure with integrated passive structures
#1626Semiconductor-on-insulator (SOI) deep trench capacitor
#1627Semiconductor device including transistor and method of manufacturing the same
#1628Method of fabricating isolated capacitors and structure thereof
#1629Electronic devices and systems, and methods for making and using the same
#1630Self-contained integrated circuit including adjacent cells of different types
#1631Semiconductor device including FinFET device
#1632LATERAL BIPOLAR TRANSISTOR AND CMOS HYBRID TECHNOLOGY
#1633Recessed single crystalline source and drain for semiconductor-on-insulator devices
#1634SOI device with embedded liner in box layer to limit STI recess
#1635Deep trench capacitor
#1636DRAM with dual level word lines
#1637Electrical isolation structures for ultra-thin semiconductor-on-insulator devices
#1638Semiconductor device including an active region and two layers having different stress characteristics
#1639Dynamic random access memory unit and method for fabricating the same
#1640Methods for forming semiconductor device structures
#1641Techniques for gate workfunction engineering to reduce short channel effects in planar CMOS devices
#1642Semiconductor device and method of manufacturing the same
#1643Substrate structure and method for manufacturing same
#1644Techniques for gate workfunction engineering to reduce short channel effects in planar CMOS devices
#1645Method and structure for integrating capacitor-less memory cell with logic
#1646Thin integrated circuit chip-on-board assembly and method of making
#1647Semiconductor device structures and methods of forming semiconductor structures
#1648Trap rich layer with through-silicon-vias in semiconductor devices
#1649Semiconductor structure having NFET extension last implants
#1650Semiconductor device and production method
#1651Semiconductor structures and devices
#1652Transistor structures and integrated circuitry comprising an array of transistor structures
#1653Semiconductor-on-insulator (SOI) structure with selectivity placed sub-insulator layer void(s) and method of forming the SOI structure
#1654Integrated circuit including transistor structure on depleted silicon-on-insulator, related method and design structure
#1655DRAM with dual level word lines
#1656Integrated circuit having memory cell array including barriers, and method of manufacturing same
#1657Charge breakdown avoidance for MIM elements in SOI base technology and method
#1658Self-protected metal-oxide-semiconductor field-effect transistor
#1659Semiconductor device and manufacturing method thereof
#1660Field effect transistors with varying threshold voltages
#1661Hybrid computing module
#1662Radio-frequency switch system having improved intermodulation distortion performance
#1663Strained silicon and strained silicon germanium on insulator
#1664Complementary bipolar inverter
#1665DEEP TRENCH HEAT SINK
#1666Integrated semiconductor devices with single crystalline beam, methods of manufacture and design structure
#1667Strained silicon and strained silicon germanium on insulator field-effect transistor
#1668CMOS DEVICES HAVING STRAIN SOURCE/DRAIN REGIONS AND LOW CONTACT RESISTANCE
#1669Undercut insulating regions for silicon-on-insulator device
#1670Semiconductor device with epitaxial source/drain facetting provided at the gate edge
#1671Trap rich layer formation techniques for semiconductor devices
#1672Bonded substrate and manufacturing method thereof
#1673Semiconductor device, method for manufacturing same, and nonvolatile semiconductor memory device
#1674MEMORY CELL WITH ASYMMETRIC READ PORT TRANSISTORS
#1675Ultrathin body fully depleted silicon-on-insulator integrated circuits and methods for fabricating same
#1676Manufacturing process for zero-capacitor random access memory circuits
#1677Strained silicon and strained silicon germanium on insulator metal oxide semiconductor field effect transistors (MOSFETs)
#1678Semiconductor structure and method for manufacturing the same
#1679Methods of forming semiconductor devices by forming semiconductor channel region materials prior to forming isolation structures
#1680Strained thin body CMOS device having vertically raised source/drain stressors with single spacer
#1681IMPLEMENTING ISOLATED SILICON REGIONS IN SILICON-ON-INSULATOR (SOI) WAFERS USING BONDED-WAFER TECHNIQUE
#1682DRAM with a nanowire access transistor
#1683Method for manufacturing semiconductor device
#1684Process for fabricating an integrated circuit having trench isolations with different depths
#1685Method and structure providing optical isolation of a waveguide on a silicon-on-insulator substrate
#1686Mixed orientation semiconductor device and method
#1687Retrograde substrate for deep trench capacitors
#1688MOS capacitors with a finFET process
#1689Semiconductor active matrix on buried insulator
#1690Retrograde substrate for deep trench capacitors
#1691Epitaxial semiconductor resistor with semiconductor structures on same substrate
#1692MOS capacitors with a finfet process
#1693Semiconductor active matrix on buried insulator
#1694Buried channel field-effect transistors
#1695Buried-channel field-effect transistors
#1696Method for simultaneously forming features of different depths in a semiconductor substrate
#1697Semiconductor substrate with transistors having different threshold voltages
#1698Complementary metal-oxide-semiconductor (CMOS) device and method
#1699SEMICONDUCTOR SUBSTRATE WITH TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES
#1700Semiconductor device
#1701Method of manufacturing laminated wafer by high temperature laminating method
#1702Minimizing leakage current and junction capacitance in CMOS transistors by utilizing dielectric spacers
#1703Metal-insulator-metal (MIM) capacitor with deep trench (DT) structure and method in a silicon-on-insulator (SOI)
#1704CMOS WITH SiGe CHANNEL PFETs AND METHOD OF FABRICATION
#1705CMOS WITH SiGe CHANNEL PFETs AND METHOD OF FABRICATION
#1706Diode-triggered silicon controlled rectifier with an integrated diode
#1707Capacitorless DRAM on bulk silicon
#1708BICMOS DEVICES ON ETSOI
#1709TRANSISTOR HAVING A STRESSED BODY
#1710SOI transistors with improved source/drain structures with enhanced strain
#1711MOS having a sic/sige alloy stack
#1712Integrated circuit including thermal gate, related method and design structure
#1713Pseudo butted junction structure for back plane connection
#1714Semiconductor structure having a source and a drain with reverse facets
#1715Planar polysilicon regions for precision resistors and electrical fuses and method of fabrication
#1716Structure and method of high-performance extremely thin silicon on insulator complementary metal—oxide—semiconductor transistors with dual stress buried insulators
#1717Robust isolation for thin-box ETSOI MOSFETS
#1718Solar-powered energy-autonomous silicon-on-insulator device
#1719Nonvolatile memory device and method of fabricating the same
#1720Structure and method to improve ETSOI MOSFETS with back gate
#1721Semiconductor device and structure
#1722Integrated circuit diode
#1723Single poly electrically erasable programmable read only memory (single poly EEPROM) device
#1724Nickelide source/drain structures for CMOS transistors
#1725Embedded DRAM for extremely thin semiconductor-on-insulator
#1726Fin field effect transistor and fabrication method
#1727Method of forming epi film in substrate trench
#1728Methods of manufacturing semiconductor devices having a support structure for an active layer pattern
#1729Semiconductor device
#1730REPLACEMENT GATE ELECTRODE WITH A TANTALUM ALLOY METAL LAYER
#1731Method of forming substrate contact for semiconductor on insulator (SOI) substrate
#1732REPLACEMENT GATE ELECTRODE WITH A TANTALUM ALLOY METAL LAYER
#1733Manufacturing method for a device with transistors strained by silicidation of source and drain zones
#1734MOSFET with work function adjusted metal backgate
#1735Circuit and system of using junction diode as program selector and MOS as read selector for one-time programmable devices
#1736Method of manufacturing semiconductor device and semiconductor device
#1737Semiconductor devices having stressor regions and related fabrication methods
#1738Integrated circuit having raised source drains devices with reduced silicide contact resistance and methods to fabricate same
#1739Junction butting on SOI by raised epitaxial structure and method
#1740Flash memory and method for fabricating the same
#1741Multi-layer metal support
#1742Extremely thin semiconductor-on-insulator (ETSOI) layer
#1743Semiconductor substrate for manufacturing transistors having back-gates thereon
#1744Semiconductor device
#1745Trench capacitor with spacer-less fabrication process
#1746Semiconductor arrangement with active drift zone
#1747Method to enable the formation of silicon germanium channel of FDSOI devices for PFET threshold voltage engineering
#1748Semiconductor arrangement with active drift zone
#1749Transistor with counter-electrode connection amalgamated with the source/drain contact
#1750Semiconductor device
#1751Epitaxial replacement of a raised source/drain
#1752Electrical signal isolation and linearity in SOI structures
#1753Selective amorphization for electrical signal isolation and linearity in SOI structures
#1754Integrated circuit including DRAM and SRAM/logic
#1755Integrated circuit with a thin body field effect transistor and capacitor
#1756Thermally stable high-K tetragonal HFOlayer within high aspect ratio deep trenches
#1757Integrated Circuit Having Back Gating, Improved Isolation And Reduced Well Resistance And Method To Fabricate Same
#1758Structure and method for using high-K material as an etch stop layer in dual stress layer process
#1759REDUCTION OF CONTACT RESISTANCE AND JUNCTION LEAKAGE
#1760Integrated circuit having raised source drains devices with reduced silicide contact resistance and methods to fabricate same
#1761Low series resistance transistor structure on silicon on insulator layer
#1762Electrical isolation structures for ultra-thin semiconductor-on-insulator devices
#1763SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
#1764Integrated circuit having raised source drains devices with reduced silicide contact resistance and methods to fabricate same
#1765Integrated circuit with a thin body field effect transistor and capacitor
#1766Integrated circuit including DRAM and SRAM/logic
#1767Integrated circuit including DRAM and SRAM/logic
#1768SYSTEMS AND METHODS FOR BACKSIDE THRESHOLD VOLTAGE ADJUSTMENT
#1769Self aligned structures and design structure thereof
#1770CMOS having a SiC/SiGe alloy stack
#1771THIN FILM TRANSISTOR AND FABRICATING METHOD
#1772Structure, method and system for complementary strain fill for integrated circuit chips
#1773REDUCTION OF THICKNESS VARIATIONS OF A THRESHOLD SEMICONDUCTOR ALLOY BY REDUCING PATTERNING NON-UNIFORMITIES PRIOR TO DEPOSITING THE SEMICONDUCTOR ALLOY
#1774Method for improved mobility using hybrid orientation technology (HOT) in conjunction with selective epitaxy and related apparatus
#1775Methods for the fabrication of integrated circuits including back-etching of raised conductive structures
#1776V-groove source/drain MOSFET and process for fabricating same
#1777V-groove source/drain MOSFET and process for fabricating same
#1778Transistor, method for fabricating the transistor, and semiconductor device comprising the transistor
#1779RAM memory cell comprising a transistor
#1780Integrated circuits formed on strained substrates and including relaxed buffer layers and methods for the manufacture thereof
#1781Method and structure for forming ETSOI capacitors, diodes, resistors and back gate contacts
#1782Method of replacing silicon with metal in integrated circuit chip fabrication
#1783Semiconductor structure and method for forming the semiconductor structure
#1784Integrated circuit assembly and method of making
#1785Structure and method to fabricate a body contact
#1786Noble gas implantation region in top silicon layer of semiconductor-on-insulator substrate
#1787Borderless contact for ultra-thin body devices
#1788Polysilicon/metal contact resistance in deep trench
#1789Method, structure and design structure for customizing history effects of SOI circuits
#1790Semiconductor-on-insulator with back side body connection
#1791Integrated semiconductor devices with single crystalline beam, methods of manufacture and design structure
#1792Method for developing a custom device
#1793Integrated semiconductor devices with amorphous silicon beam, methods of manufacture and design structure
#1794Methods of manufacturing integrated semiconductor devices with single crystalline beam
#1795Semiconductor device and method of manufacturing the same
#1796Semiconductor device
#1797Prevention of ILD Loss in Replacement Gate Technologies by Surface Treatmen
#1798Radiation hardened memory cell and design structures
#1799Liquid crystal display device and electronic device
#1800Recessed single crystalline source and drain for semiconductor-on-insulator devices